Tektronix 1L30, Инструкция по эксплуатации

Страница: 30 / 129

^ r V i . i - i ^ :7i^^ifi^n-^irr> ■ i
The phase detector samples the instantaneous RF voltage
generated by the tunable local oscillator at a rate deter­
mined by .the reference frequency. The sample voltages are
then integrated and applied to a comparator which gener­
ates a corrective voltage to feed back to the local oscillator.
When the local oscillator frequency is an exact multiple
of the reference frequency, the phase detector output be­
comes a DC voltage that is proportional to the instantan­
eous potential of the sampled oscillator voltage. If the phase
of the local oscillator frequency should drift, the phase de­
tector output will change. This change is amplified through
Q 860-Q870 and applied as a cdrrective voltage to a volt­
age controlled capacitance diode in the oscillator tuned
circuit. This corrects or shifts the phase of the oscillator so
that it remains phase locked to the reference frequency. See
Fig. 3-2 and Fig. 3-3.
The corrective signal from the comparator and amplifier
is also applied to the vertical circuit when the LOCK CHECK
button SW889 is depressed. This provides a beat frequency
signal indication on the CRT so the operator can locate a
lock point, and phase lock operation will occur. Beat fre­
quency displays appear on the CRT screen as the locai
oscillator is tuned (see O perating section). A reference volt­
age related to the position of the FINE RF CENTER FREQ
control is also applied to the vertical deflection circuit and
is used to estabilsh the dynamic operating range for the com­
parator amplifiers Q 860-Q 870. Phase lock operation should
be set within the dynamic range of the amplifiers. This
dynamic range is within the center 4 cm of the graticule
window.
The reference frequency (either the internal 1 M Hz signal
from Q800-Y800 or the external REF FREQ IN signal) is
converted to a train of positive trigger pulses by the trigger
generator circuit of Q820. Q 820 is part of a blocking oscil­
lator circuit. In .its quiescent state the transistor is turned on
by the forward bias on its base circuit. As the input signal
Circuit Description— Type 1L30
swings negative, D821 turns on, pulling the transistor base
down. The emitter of Q820 follows the base down, reducing
the current in transformer T820. This couples this change back
to the base circuit of Q820, causing regeneration. The tran­
sistor turns off in approximately 2 or 3 nanoseconds; The
third transformer winding of T820 couples the resulting pos*.
itive-going trigger pulse through D841 to the base of the
avalanche transistor Q840.
The quiescent voltage of Q840 is set by the Avalanche
Volts adjustment R831 in the base voltage divider circuit
of Q830. This sets the avalanche voltage requirements for
Q840. The positive portion of the pulse from the transformer
T820 triggers Q840 into avalanche, and the resulting col­
lector current of Q840 sweeps out the stored charge .of the
snap-off diode D846. When the charge has dissipated, the
recovery pulse of the diode generates a fast negative-going
recovery step which is differentiated and coupled through
C847 to the etched circuit transmission line transformer T856-
T857.
These transformers provide a 2:1 voltage stepup and con­
verts the single-ended input signal of the snap-off diode to .a
push-pull balanced output signal across the phase detector
diodes. Refer to the swept oscillator description for the dis­
cussion on the transformer operation.
The phase detector (Fig. 3-3) consists of two diode gate
and low-pass filter. The diodes are reverse biased so the
local oscillator signal that is applied to the junction of the
diodes will not turn the diodes on. Equal amplitude and
opposite polarity strobe pulses of short duration from the
pulse forming circuit are applied to the opposite ends of the
diodes. These pulses gate the diodes on for the short strobe
pulse period.
The voltage at the junction of the two resistors will be the
summation of the strobe pulse, plus the instantaneous value
of the oscillator voltage. However, since the strobe pulses
tv.
I:
P
r
(; ■
I'
t:
r
I;.
i
t '
k.
©
3-3
Fig. 3-2. Phase lock block diagram.