TDI XBL 400, Инструкция по эксплуатации и программированию

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Status and Event Registers —Status Structure
The Status Logic illustration shows the logical relationship between the status registers. Three
of the registers, the condition (CON) register, the error (ERR) register, and the status (STA)
register reflect the condition of the load.
Two of the registers, the fault shutdown mask (SDN) and the fault latch mask (LAT) control
which of the condition register bits cause a load shutdown (shutdown mask) and/or are latched
until read (latch mask).
The summary bit enable (SBE) register controls, which condition bits, are passed through to the
system status register (STA). The system status register is available either in response to an
STA? query
The service request (SRQ) enable mask controls which bits in the status register can assert the
SRQ line. Additional information about the registers appears in tables that follow.
Refer to the CON?, ERR?, LAT, SBE, SDN, SRQ and STA? in the Detail Language Elements
section of Chapter 3 for additional information about the specific registers.
Condition, Latch, Shutdown and Summary Bit Enable Registers
Bit Mnemonic Interpretation
7 UV Indicates an under voltage condition
6 OV Indicates an over voltage condition
5 OT Indicates an over temperature condition
4 GPIB ERROR Indicates a GPIB bus error
3 OC Indicates current limit condition
2 OP Indicates a power limit condition
1 SAT Indicates a load or module saturation condition
0 MOD Indicates a module level fault
Error Register
Bit Mnemonic Interpretation
7 Reserved Reserved for future use.
6 Reserved Reserved for future use.
5 Not allowed The received command is not permitted in the loads
present state. For example, a LOAD ON in the face
of a HARDWARE FAIL.
4 Too long The program line length exceeds the loads input
buffer.
3 Numeric A number has been received that can not be
interpreted for example, 3.14A2 instead of 3.14.
2 Reserved Reserved for future use.
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