Systran SCRAMNet+ VME3U, Справочник по аппаратуре

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DESCRIPTION
Copyright 1995, S
YS
I
RAN
Corp. 3-3 VME3U H/W REFERENCE
cases, the mode of operation is set during initialization and remains unchanged during run
time. The CSRs are described in detail in Section 5.
3.2.3 Virtual Paging
All SCRAMNet
+
nodes use the same 8 MB shared memory map. This feature permits
different SCRAMNet
+
boards with 4 MB of shared memory or less to be paged into
different sections of the 8 MB memory map. A board with a 4 MB or smaller memory
may be located on any shared memory address boundary that is an even multiple of itself
(e.g. 2 MB can page to 0, 2, 4 or 6 MB address).
3.3 FIFO Buffers
The SCRAMNet
+
board contains various FIFO buffers used for temporarily storing
information during normal send and receive operation of the node. Refer to Figure 3-1.
3.3.1 Transmit FIFO
The Transmit FIFO is a message holding area for native messages waiting to be
transmitted. Each host write to SCRAMNet
+
memory may constitute a WRITE to the
Transmit FIFO. (Data Filtering and HIPRO features may interfere with this.) Each
WRITE to the Transmit FIFO contains 21 bits of address (A22-A2), 32 bits of data, and
one bit of interrupt information. The Transmit FIFO can hold up to 1024 WRITEs before
becoming full.
The Transmit FIFO has a 7/8 Full condition indicator (CSR1, bit 2 ON). When the
Transmit FIFO reaches a FULL condition (CSR1, bit 0 ON), one more host WRITE
could cause a message to be lost. To prevent this, the CSR-controllable, built-in
SCRAMNet
+
feature called VME Holdoff extends the computer WRITE cycle until the
Transmit FIFO is able to empty at least one message.
3.3.2 Transceiver FIFO
This buffer is used to receive foreign messages from the network, and send them on, or to
hold received foreign messages while inserting a native message from the host onto the
network.
Each node is responsible for receiving foreign messages, writing them to its copy of
shared memory, and re-transmitting the message to the next node.
3.3.3 Interrupt FIFO
The Interrupt FIFO contains a 21-bit address (A22 - A2) and a retry status bit for each
shared-memory-based interrupt received. The Interrupt FIFO can hold 1024 interrupt
addresses. This FIFO can be read using CSR4 and CSR5.
3.3.4 Receiver FIFO
The Receiver FIFO is designed as a temporary holding place for incoming foreign
messages while the shared memory is busy servicing a host request. This FIFO is three
messages deep, and is designed so it can never be overrun. Each item in the Receiver
FIFO contains 21 bits of address (A22 - A2), 32 bits of data, and one incoming interrupt
bit. When the messages are 1024 bytes, the initial header information data stays in the
FIFO, the subsequent 4 bytes of data are loaded in, and the address is incremented by
four.