Systran SCRAMNet+ VME3U, Справочник по аппаратуре

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HOST ACCESS TIMING
Copyright 1995, S
YS
I
RAN
Corp. D-1 VME3U H/W REFERENCE
D.1 Introduction
The S host access timing is comprised of three separate module timings.
•
Dual-Port RAM Controller (DPRC).
•
Host Interface Logic to shared memory/CSR.
•
Host Interface Logic to host-specific CSR.
The first module allows shared memory to be updated by the high speed serial network
without utilizing valuable CPU bus bandwidth. The second module is needed to interface
shared memory and the ASIC internal CSRs to the host CPU bus. The third module is
needed to interface the host-specific external CSRs to the host CPU.
D.2 Dual-Port RAM Controller Module
S memory is controlled by the DPRC. The DRPC has two ports: one for
host access and one for network access. The DPRC arbitrates requests for these two ports
on a first come, first serve basis. In case of a tie, the high speed serial network has
priority. The first port, which is enabled for READ/WRITE, is connected to the host
CPU. The second port is WRITE ONLY and is connected to the high speed serial
network. There are three types of accesses to the DPRC. They are shown in Table D-1.
Table D-1 Dual Port RAM Controller Access Types
Access Type Port Cycle
Time
Host WRITE 1 240 ns
Host READ 1 133 ns
Network WRITE 2 133 ns
D.2.1 Contention
The S Network, being an intelligent peripheral, does buffered WRITEs to
shared memory. This speeds up host WRITEs by latching the data and address when a
host WRITE is detected, and then replying to the host immediately without waiting for
the DPRC to finish the WRITE activity. Since the WRITE buffering is only one level
deep, it is possible that on back-to-back accesses the second access will be delayed until
the buffer is available (i.e., when the current DPRC cycle is finished).
This phenomenon results in the stretching of two types of cycles outside the normal case:
•
Back-to-Back WRITE cycle. In this cycle the second reply on the bus is held
off until the first WRITE cycle has finished.
•
WRITE cycle followed by a READ cycle. In this case the READ cycle is
delayed from starting until the previous WRITE cycle is completed.
F
NOTE: The cases resulting in stretched cycles describe a very fast host bus
condition and are not normal. In reality, SCRAMNet
+
memory was designed and
optimized for CPU data storage. Therefore CPU activities such as instruction
fetches, instruction execution, and other miscellaneous activities will ensure the
phenomenon of cycle stretching will rarely, if ever, occur.