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Synopsys, Inc.

5.60a

March 2020

Setting Up Software Environment

PCIe IP Prototyping Kit Installation Guide

2.1

Licensing and Tool Requirements

The following table lists the licenses and tools needed for extracting the release package, rebuilding the

Linux environment and configuring and rebuilding the FPGA image.

For the buildroot requirements, see

The Buildroot User Manual

chapter “System Requirements”.

Table 2-1

Licensing and Tools Requirements

License/Tool

Version

Description

Extracting the Release Package

DWC-PCIE

DWC-PCIE-G

<gen>-

PREM-A-SRC

<gen>

depends on the PCIe Generation of the design. For example, for PCIe

Gen3 configurations, license DWC-PCIE-G3-PREM-A-SRC is required.

Rebuilding Linux Environment

gmake

3.82

GNU Make is used to control, and build executable programs using the
program’s source files, and by reading the makefiles.

GCC

5.2.0

GNU Compiler Collection is a compiler system that supports various
programming languages.

tcl

8.5.12

Tclsh is a shell-like application that reads and evaluates Tcl commands from a
standard input or from a file.

Configuring and Rebuilding FPGA Image

CoreConsultant

(coreTools)

2019.06-SP2

The Synopsys coreConsultant tool facilitates design reuse by providing
reliable, error-free design configuration and high-quality synthesis of reusable
cores.

VCS (VCS VCSi)

2018.09-SP2

VCS provides industry-leading performance and capacity, complemented by a
complete collection of advanced methodology-aware testbench and constraint
debug features, bug-finding, coverage, planning and assertion technologies.

Design Compiler
(Synthesis)

2016.03-SP4

Design Compiler helps RTL designers perform a “what-if” analysis of floorplan
quickly and efficiently so that they can be ensured that the design meets its
targets during physical implementation without requiring iterations.

HAPS
ProtoCompiler
(ProtoCompiler)

2018.09-4

ProtoCompiler tool combines hardware and software, and provides a
comprehensive and streamlined solution for prototyping single-FPGA designs
which target the Xilinx Virtex-7 and UltraScale FPGA family.

a

Xilinx Vivado

2018.1

The Vivado

®

Design Suite is designed to improve productivity. This entirely

new tool suite is architected to increase the overall productivity for designing,
integrating, and implementing with the Xilinx

®

7 series, Zynq

®

-7000 All

Programmable (AP) SoC, and UltraScale™ devices.

DesignWare Products

DWC_pcie_ctl

5.60a

The DesignWare PCI Express controller provides a solution to implement a
PCI Express port for a PCI Express root complex or endpoint application.

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Содержание DesignWare 826-0

Страница 1: ...5 60a March 2020 DesignWare PCIe IP Prototyping Kit Installation Guide dw_ipk_dwipk_pcie Product Codes E826 0 E825 0 C368 0 C369 0 C046 0 E025 0 E026 0 E027 0 E827 0 E828 0...

Страница 2: ...sibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDIN...

Страница 3: ...nt 33 2 1 Licensing and Tool Requirements 34 2 2 Setting License File Environment Variable 36 2 3 Installing dw_ipk_dwipk_pcie 37 2 3 1 Setting Up Your Environment 37 2 3 2 Extracting the Release Pack...

Страница 4: ...4 Synopsys Inc SolvNetPlus DesignWare 5 60a March 2020 Contents PCIe IP Prototyping Kit Installation Guide...

Страница 5: ...rapidly develop test and debug IP software before SoC availability The kit is a complete and stand alone solution that requires minimal configuration This document provides the necessary information t...

Страница 6: ...en3 Root Complex Controller on HAPS 80 C10 PHY AXI tunnel to ARC SDP E026 0 DesignWare PCIe Gen3 Root Complex Controller on HAPS 80 Xilinx Gen3 PHY AXI tunnel to ARC SDP E027 0 DesignWare PCIe Gen3 En...

Страница 7: ...for the kits using Synopsys PHY on HAPS 80 Figure 1 1 PCIe Root Complex IP Prototyping Kit Components with Synopsys PHY on HAPS 80 Attention All PCIe IP Prototyping Kits were developed for use with HA...

Страница 8: ...ponents for the kits using Synopsys PHY on HAPS 80 Figure 1 3 shows the PCIe Root Complex IP Prototyping Kit recommended components for the kits using the Xilinx PHY on HAPS 80 Figure 1 2 PCIe Endpoin...

Страница 9: ...typing Kit Installation Guide Setting Up Hardware Components Figure 1 3 PCIe Root Complex IP Prototyping Kit Components with Xilinx PHY on HAPS 80 Figure 1 4 shows the PCIe Endpoint IP Prototyping Kit...

Страница 10: ...5 60a March 2020 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1 4 PCIe Endpoint IP Prototyping Kit Components with Xilinx PHY on HAPS 80 HAPS 80 SD Card PCIE 8_PDL...

Страница 11: ...psys Inc 11 SolvNetPlus DesignWare 5 60a March 2020 PCIe IP Prototyping Kit Installation Guide Setting Up Hardware Components Figure 1 5 PCIe Endpoint IP Prototyping Kit Components with E32 PHY on HAP...

Страница 12: ...totyping Kit Recommended Components and Part Numbers Quantity Part Number Item Description DesignWare PCIe Gen4 Root Complex Controller on HAPS 80 E16 PHY AXI tunnel to ARC SDP E826 0 1 HW0352 000 HAP...

Страница 13: ...Gen3 PHY Board Synopsys C10 PHY Board PCIe Gen3 PHY 1 3052113 SD Card TRANSCEND TS2GSDC CARD DesignWare PCIe Root Complex Controller on HAPS 80 C10 PHY AXI tunnel to ARC SDP E026 0 1 HW0352 000 HAPS 8...

Страница 14: ...CIE 4 PC Four lane PCI Express card with PC connection PCIE 4 Cable Four lane connection cable 2 HW0039 0 CON_CABLE_25_HT3 HT3 Cables 1 N A PCIe Backplane Rev C PCIe Root Complex Endpoint Backplane De...

Страница 15: ...mponents a 3MTM Part Number b To perform Precision Time Measurement PTM tests use the PCIE 8_PDL_MGB card to connect the HAPS board to the Motherboard or PTC card The PCIE 4 MGB Kit has an embedded PC...

Страница 16: ...rform the following tasks 1 Insert the SD card containing the FPGA build files in the HAPS 80 board The SD card slot is located in the Front Panel see Figure 1 7 Figure 1 7 Detail of the HAPS 80 Front...

Страница 17: ...Hardware Components 3 Remove the locker pin and the four screws holding the MGB shelves see Figure 1 8 Figure 1 8 Detail of the HAPS 80 MGB Shelves 4 Remove the MGB Shelves from the HAPS 80 and insert...

Страница 18: ...on the HAPS 80 and ports P1 P6 on the C10 PHY to mechanically connect the boards If you re using a E16 PHY use HT3 ports J5 J10 on the HAPS 80 and ports P1 P6 on the E16 PHY Figure 1 10 illustrates t...

Страница 19: ...Second HT3 cable to the HAPS 80 board on the HT3 track 7 Xilinx PHY or track 24 C10 or E16 d Other end of the second HT3 to the ARC SDP HT3 track J4 2 Insert the SD card containing the Linux image in...

Страница 20: ...e using a Synopsys PCIe PHY1 connect the PCIe PHY board to the PCIe Root Complex slot c Connect the PCIe endpoint device to the PCIe Endpoint slot d If you are using the Xilinx PHY connect the Paddle...

Страница 21: ...Appendix A Status LEDs section A 2 The LED marked UDONE indicates if the FPGA is configured 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 SW2501 OFF ON SW2503 OFF ON SW2502 OFF ON SW2504 SW2507 SW2506...

Страница 22: ...PCIe Backplane board by turning on the ATX power supply f The HAPS 80 board LED1 turns green to indicate the PCIe link connection see Appendix A Status LEDs section A 2 Figure 1 13 illustrates the as...

Страница 23: ...onents Figure 1 14 PCIe Root Complex IP Prototyping Kit Setup Using a C10 PHY Board and HAPS 80 If you are using the Synopsys PHY board connect the Synopsys PHY board to the PCIe Root Complex slot of...

Страница 24: ...psys Inc SolvNetPlus DesignWare 5 60a March 2020 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1 15 PCIe Root Complex IP Prototyping Kit using the E16 PHY Board and...

Страница 25: ...and your computer 2 Connect the E32 PHY card to HAPS 80 a Use HT3 ports 20 21 22 and 23 on the HAPS 80 and HT3 ports 4 3 2 and 1 respectively on the E32 PHY And also HT3 8 9 10 and 11 on the HAPS 80 a...

Страница 26: ...s DesignWare 5 60a March 2020 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide Figure 1 16 PCIe Root Complex IP Prototyping Kit using the E32 PHY board and HAPS 80 Figure 1 17...

Страница 27: ...oard Connect the HAPS 80 power supply During the power up sequence the supervision LEDs RESET READY ALERT and PWR change color After a successful power up sequence all LEDs must be green see Status LE...

Страница 28: ...rototyping Kit Installation Guide Figure 1 18 PCIe Gen3 Endpoint IP Prototyping Kit Setup Using a Synopsys C10 PHY Figure 1 19 illustrates the assembled PCIe Endpoint IP Prototyping Kit using the E16...

Страница 29: ...uide Setting Up Hardware Components Figure 1 19 PCIe Endpoint IP Prototyping Kit using the E16 PHY To setup the HAPS 80 board for the PCIe Endpoint IP Prototyping Kit using Xilinx PHY refer to Setting...

Страница 30: ...8 respectively on the E32 PHY to mechanically connect the boards 2 Complete the following hardware power up sequence to ensure proper inter board communication a Power up the HAPS 80 board Connect th...

Страница 31: ...Synopsys Inc 31 SolvNetPlus DesignWare 5 60a March 2020 PCIe IP Prototyping Kit Installation Guide Setting Up Hardware Components Figure 1 22 Connection between HAPS 80 and E32 PHY...

Страница 32: ...32 Synopsys Inc SolvNetPlus DesignWare 5 60a March 2020 Setting Up Hardware Components PCIe IP Prototyping Kit Installation Guide...

Страница 33: ...it hardware components you must set up the software environment This chapter provides the required steps for setting up your environment to use a prototyping kit The following topics are described Lic...

Страница 34: ...s coreConsultant tool facilitates design reuse by providing reliable error free design configuration and high quality synthesis of reusable cores VCS VCS VCSi 2018 09 SP2 VCS provides industry leading...

Страница 35: ...with any combination of different data port widths different clock frequencies and different endianness DW_axi_gm 2 03a The DW_axi_gm is a configurable module between a generic interface GIF and an A...

Страница 36: ...license server setenv SNPSLMD_LICENSE_FILE SNPSLMD_LICENSE_FILE my_license_file port host or setenv LM_LICENSE_FILE LM_LICENSE_FILE my_license_file port host 2 Verify the license setup echo LM_LICENS...

Страница 37: ...ains the dwh_update dwh_install and dw_vip_setup scripts These scripts provide important diagnostic information in about the version of your DWC component s 2 3 2 Extracting the Release Package The PC...

Страница 38: ...r the Workspace Click OK to create a workspace 5 Complete the Specify Configuration activity using the default parameter values Click Apply in the Specify Configuration dialog This creates the RTL for...

Страница 39: ...ar folder structure The folder content is created after you create a coreConsultant workspace Table 2 2 Prototyping Kit Directory Structure Description Directory Sub directory Description Top level di...

Страница 40: ...h as well as several test cases software Software drivers and files directory with a fully functional pre built Linux image phy Xilinx PHY files Note Note Note Note After you set up the PCIe IP Protot...

Страница 41: ...ware components and software environment you can use the example application that is provided in the prototyping kit to test the setup This chapter describes the steps for connecting to ARC SDP or ARC...

Страница 42: ...exe file that does not require installation Example To run PuTTY 1 Connect the USB standard B cable from the ARC USB connector to the PC If you are using an ARC HSDK connect a micro USB cable from th...

Страница 43: ...he USB Serial Port number for example COM4 as shown in Figure 3 1 Figure 3 1 Device Manager Window 3 In the PuTTY configuration window use the following configuration parameters Before typing the conf...

Страница 44: ...stallation Guide Figure 3 2 PuTTY Configuration 4 Save the configuration parameters using the Sessions feature Type a session name for example ARC as shown in Figure 3 2 and click Save 5 To start a se...

Страница 45: ...The Adept driver is included in the axs101_tools_ version zip file which is available on the ARC SDP download web site You should have received the corresponding URL when you purchased the PCIe IP Pr...

Страница 46: ...Hardware Components on page 5 2 Restart the ARC SDP system board by pressing the Board RESET button located next to the power connector see Figure 3 3 The Linux Kernel boots up Figure 3 3 ARC SDP Boa...

Страница 47: ...0a March 2020 A Status LEDs This chapter provides information about the PCIe IP Prototyping Kit LEDs The following topics are described HAPS 80 Supervision LEDs on page 48 HAPS 80 Power Up Sequence on...

Страница 48: ...tion Figure A 1 HAPS 80 LEDs Location Table A 1 describes the HAPS 80 supervision LEDs colors and the status they indicate The following list represents the color code for the supervision LEDs Green A...

Страница 49: ...y Supervisor power OK 12 V ALERT FPGA configuration in progress No alert FPGA temperature over limit PWR Power FPGA power off FPGA power OK FPGA power failure SVDONE Supervisor is configured UDONE FPG...

Страница 50: ...n LEDs Table A 2 indicates the different stages during the HAPS 80 power up procedure and associated LED color code Green Amber Red Unlit Table A 2 HAPS 80 Power up Supervision LEDs LED Power up Proce...

Страница 51: ...OK ERROR Stop Supervisor Firmware Check and Load OK Error Stop Power Modules Check OK Error Stop Slave Systems Version Check OK Error Stop Startup Project Load Yes No Continue Startup Project Loaded S...

Страница 52: ...peration Reset is active TEMP Indicates the FPGA temperature status FPGA temperature is OK FPGA temperature higher than 75 C 167 F Switch OFF the board Blinking FPGA temperature higher than 90 C 194 F...

Страница 53: ...lays Control Bit Description SWPORTB_DR 23 16 Controls the upper seven segment display A segment of the display is ON when its control bit is set to 1 SWPORTB_DR 31 24 Controls the lower seven segment...

Страница 54: ...be controlled through the I O expander using the on board I2C bus Table A 5 ARC HSDK Status and System LEDs LED Color Description RST red Reset LED this LED turns red if the ARC HSDK is in Reset TUN g...

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