FIFO DATA PACKETS
Symmetricom, Inc.
bc620/627AT Time and Frequency Processor
4-5
The TFP divides the reference frequency input (whether input from an external 10 MHz source
or the on-board 10 MHz VCXO) to produce a 1pps pulse. This pulse is compared to the
reference 1pps epoch which is derived from the selected time reference (i.e., time code, external
1pps etc.). The D/A voltage is adjusted to steer the 1pps derived from the voltage controlled
oscillator into phase coherence with the reference 1pps.
Some users may wish to control the D/A converter directly. Packet “D” is provided for this
purpose. The format is as follows:
byte 1
SOH.
byte 2
“D.”
byte 3
ASCII “0” - “F” (bits 12 through 15)..
byte 4
ASCII “0” - “F” (bits 8 through 11).
byte 5
ASCII “0” - “F” (bits 4 through 7).
byte 6
ASCII “0” - “F” (bits 0 through 3).
byte 7
ETB.
The bc620 firmware routines which normally load the D/A (i.e. disciplining) must be disabled
using the path packet “P” to prevent the bc620 from overwriting the data input with this packet
(“D”).
The bc620.c file has an example function, preset_DA( ), which presets the D/A as described
above.
4.1.5 PACKET “F” - HEARTBEAT (PERIODICS) CONTROL
The programmable frequency output is a very powerful bc620/627AT feature. Feedback from
the users of other board level products motivated the inclusion of a very comprehensive periodic
programming capability. Rates from 2.5 MHz to 2.3 MHz are easily achieved.
The heartbeat engine of the bc620/627AT consists of two sections of an INTEL 82C54
programmable interval timer connected in a serial configuration and driven by the TFP 10 MHz
reference. Glue logic in one of the logic cell arrays supports both synchronous (with the 1pps
epoch) and asynchronous operation. It is helpful (although not essential) to read the INTEL data
sheet on the 82C54. Packet “F” allows the user complete access to the serial counters using
standard INTEL loading protocols.
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