SOFTWARE INTERFACE
Symmetricom, Inc.
bc620/627AT Time and Frequency Processor
3-9
1 PPS (Bit 1)
This bit is set by the TFP once each second with the rising edge of the on-time 1pps output pulse.
The user is responsible for clearing the bit.
FIFO RDY (Bit 2)
The 620AT sets this bit when an output FIFO data packet is ready to be read by the host.
EF/CLR FIFO (Bit 4)
A read of this bit returns the output FIFO empty flag status. When reading data from the FIFO
this bit is monitored to insure all the FIFO data is read. The bit is clear (zero) when the FIFO is
empty.
Writing a one to this register bit clears the output FIFO of all data and sets the empty flag to
zero.
FIFO PACKET RDY (Bit 7)
Writing a one to this bit causes the TFP to take action on the input FIFO packet data.
Note
: Acknowledge register bits 0, 1, 2 are cleared by writing a one to that bit location. For
example, writing the value 0x01 to ACK will clear bit 0 and leave bit 1 unaltered.
Writing the value 0x03 to ACK will clear both bit 0 and bit 1.
Table 3-5
ACK Acknowledge Register
bit#
CONTROL
FUNCTION (SET = “1” = high voltage CLEAR = “0” = low
voltage).
0
TFP
HOST
SETS bit to acknowledge the receipt of a valid input packet from host.
CLEARS bit by writing to this register with bit 0 SET.
1
Reserved.
2
TFP
HOST
SETS bit when output FIFO contains a data packet.
CLEARS bit by writing to this register with bit 2 SET.
This bit can generate an interrupt. (See Section 3.1.7.)
3
Reserved.
4
TFP
HOST
SETS bit if output FIFO contains data. CLEARS bit if output FIFO
empty.
CLEARS output FIFO by writing to this register with bit 4
SET.
5
Reserved.
6
Reserved.
7
HOST
Must write to this register with bit 7 SET to cause TFP to take
action on the data packet previously written to the input FIFO.
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