CHAPTER THREE
3-2
bc620/627AT Time and Frequency Processor
Symmetricom, Inc.
3.1 REGISTERS
This section describes the registers used on the TFP for controlling its operation and transferring
time data. Section 3.2 details the use of these registers. There are two 16-byte pages of registers
on the TFP. The page select register determines the active page and is always accessible. The
memory map for the TFP is listed in Table 3-1 and Table 3-2 (PAGE 1 registers). The first
column of these tables shows the offset from the base address of each register. The second
column (R/W) lists the access type of each register. These registers may be read only (R), write
only (W), or read/write (R/W). In some cases, a read/write register is structured to support
dissimilar data in the read and write directions. The contents of each register following a power-
on or software reset is shown (RESET VALUE). A reset value of “---” indicates that the register
contents are undefined. A label for each register is listed, as well as a brief description of the
register's function.
3.1.1 PAGE SELECT REGISTER (PAGE 0/1)
The page select register is used to activate one of two 16-byte banks of registers. Bit 0 of PAGE
selects PAGE 0 or PAGE 1, bits 1-7 are ignored during writes and undefined during reads.
PAGE is always accessible.
3.1.2 TIMEREQ AND TIME0 - TIME7 REGISTERS (PAGE 0)
Reading the TIMEREQ register causes the current time (days - microseconds) and status to be
loaded into a bank of registers, freezing the time at the instant the TIMEREQ register is
accessed. Special circuitry prohibits the time from being latched while the time is changing.
This circuitry is designed so that the TIME0 - TIME7 registers can be read immediately after a
read of the TIMEREQ register without having to wait some predetermined amount of time
(latency) for the time registers to become valid. This is referred to as zero latency time access.
A bank of 8 byte-wide registers (TIME0 - TIME7) holds the captured time and status. The time
data is in a packed BCD format as shown in Table 3-3. The time is maintained in these registers
until the TIMEREQ register is read again.
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