FIFO DATA PACKETS
Symmetricom, Inc.
bc620/627AT Time and Frequency Processor
4-7
* * * IMPORTANT * * *
When Mode 5 is used, the value of n1 and n2 produced by the 82C54 hardware is n1+1 and
n2+1. This is a result of the way INTEL designed the 82C54, and is unrelated to our design.
Example
: It is desired to implement 10000 counts per second synchronous with the 1pps.
mode = “5”
(synchronous)
n1+1 = 10
n2+1 = 100
(10,000,000) / (10 * 100) = 10000
Other values of (n1+1) and (n2+1) could have been used.
For example, (n1+1) = 25 and (n2+1) = 40.
byte 1
SOH.
byte 2
“F.”
byte 3
“5”
(mode).
byte 4
“0.”
byte 5
“0.”
byte 6
“0.”
byte 7
“9” (n1 = 9).
byte 8
“0.”
byte 9
“0.”
byte 10
“6.”
byte 11
“3” (n2 = 99 = 0x63).
byte 12
ETB.
The bc620.c file has an example function, load_82C54( ), illustrating the use of this packet.
4.1.6 PACKET “G” - PROPAGATION DELAY OFFSET CONTROL
It is frequently desirable to be able to program an offset into the basic timekeeping functions,
relative to the reference input. For example, if the reference input is IRIG B test range time,
there may be a significant cable propagation delay between the IRIG B source and the bc620.
This delay may be removed by simply advancing the bc620/627AT from the reference by the
known delay. The offset is programmable in steps of one-hundred nanoseconds (7 digits plus the
sign byte spans a one second range).
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