Supero X9DBL-3, Руководство пользователя

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X9DBL-i/3/iF/3F Motherboard User’s Manual
PCI Latency Timer
Use this feature to set the latency Timer of each PCI device installed on a PCI bus.
Select 64 to set the PCI latency to 64 PCI clock cycles. The options are 32,
64 , 96,
128, 160, 192, 224 and 248.
Above 4G Decoding (Available if the system supports 64-bit PCI decoding)
Select Enabled to decode a PCI device that supports 64-bit in the space above 4G
Address. The options are Enabled and
Disabled .
PERR# Generation
Select Enabled to allow a PCI device to generate a PERR number for a PCI Bus
Signal Error Event. The options are Enabled and
Disabled .
SERR# Generation
Select Enabled to allow a PCI device to generate an SERR number for a PCI Bus
Signal Error Event. The options are Enabled and
Disabled
.
Maximum Payload
Select Auto to allow the system BIOS to automatically set the maximum payload
value for a PCI-E device to enhance system performance. The options are
Auto ,
128 Bytes and 256 Bytes.
Maximum Read Request
Select Auto to allow the system BIOS to automatically set the maximum Read
Request size for a PCI-E device to enhance system performance. The options are
Auto , 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.
ASPM Support
This feature allows the user to set the Active State Power Management (ASPM)
level for a PCI-E device. Select Force L0s to force all PCI-E links to operate at L0s
state. Select Auto to allow the system BIOS to automatically set the ASPM level for
the system. Select Disabled to disable ASPM support. The options are
Disabled
,
Force L0s, and Auto.
Warning : Enabling ASPM support may cause some PCI-E devices to fail!
PCI Slot 1 OPROM, CPU1 Slot 2 PCI-E 3.0 x4 OPROM, CPU2 Slot 3 PCI-E
3.0 x8 OPROM, CPU2 Slot 4 PCI-E 3.0 x8 OPROM, CPU2 Slot 5 PCI-E 3.0 x8
OPROM, CPU1 Slot 6 PCI-E 3.0 x16 OPROM
Select Enabled to enable Option ROM support to boot the computer using a de-
vice installed on the slots specified above. The options are Enabled and Disabled.