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X9DBL-i/3/iF/3F Motherboard User’s Manual
JD1
JPW1
JIPMB1
LED3
T-SGPIO1
T-SGPIO2
JSTBY1
J9
JBT1
JPI2C1
JF1(FP Control)
TPM/Port80
JL1
JI2C1
JI2C2
JOH1
LED1
JWP1
JBR1
JPME1
JVRM_I2C1
JVRM_I2C2
JPG1
JPB1
JPL1
JPL2
JCPUVRD_SMB
I-SATA1
I-SATA0
S-SATA/
SAS0
1
7
I-SATA2
I-SATA3
I-SATA4
I-SATA5
BT1
SP1
FAN4
FAN1
FAN2
FAN5
FANA
FAN3
JPW2
JPW3
SCU-
SGPIO1
USB2/3
USB4/5
KB/MOUSE
CPU1 SLOT2 PCI-E 3.0 X4(IN X8)
CPU1
P2-DIMM1F
P2-DIMM1E
P2-DIMM1D
P1-DIMM1B
P1-DIMM1A
P1-DIMM1C
LAN2
CPU2 SLOT3 PCI-E 3.0 X8
CPU2 SLOT5 PCI-E 3.0 X8
CPU2 SLOT4 PCI-E 3.0 X8
CPU1 SLOT6 PCI-E 3.0 X16
SLOT1 PCI 33MHZ
USB6
IPMI_LAN
VGA
COM1
USB0/1
LAN1
COM2
CPU2
JWD1
BIOS
Battery
LAN CTRL
LAN CTRL
BMC CTRL
CPLD
Intel PCH
X9DBL-i/3 (F)
Rev. 1.01
LED2
JUIDB1
SCU-
SGPIO2
S-SATA/
SAS1
S-SATA/
SAS2
S-SATA/
SAS3
S-SATA/
SAS4
S-SATA/
SAS5
S-SATA/SAS6
S-SATA/
SAS7
A . T P M / P o r t 8 0
Header
B. IPMB
TPM Header/Port 80
A Trusted Platform Module/Port 80
header is located at JTPM1 to provide
TPM support and Port 80 connection.
Use this header to enhance system
performance and data security. See
the table on the right for pin defini
-
tions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3V_DUAL
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)
IPMB
A System Management Bus header
for IPMI 2.0 is located at JIPMB1.
Connect the appropriate cable here
to use the IPMB I
2
C connection on
your system.
IPMB Header
Pin Definitions
Pin# Definition
1
Data
2
Ground
3
Clock
4
No Connection
B
A
Содержание X9DBL-3
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