Supero X7SB3, Руководство пользователя

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Chapter 1: Introduction
1-9
1-2 Chipset Overview
The Intel 3210 chipset is comprised of two primary components: the Memory Con-
troller Hub (MCH) and the I/O Controller Hub (ICH9). The X7SB3/X7SB3-F provides
the performance and feature-set required for the mainstream high-performance
cluster platform (HPC) market.
Intel 3210 Memory Controller Hub (MCH)
The function of the MCH is to manage the data flow between four interfaces: the
CPU interface, the DDR2 System Memory interface, the PCI Express interface, and
the Direct Media Interface (DMI). The MCH is optimized for the Intel® Xeon® 3000
Sequence processor in the LGA775 Land Grid Array package. It supports one or
two channels of DDR2 SDRAM.
Intel ICH9 System Features
The I/O Controller (ICH9) provides the data buffering and interface arbitration re-
quired for the system to operate efficiently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the connection between the MCH and the ICH9. The ICH9 supports two
PCI-Express devices, two Serial ATA ports, and up to eight USB 2.0 ports/head-
ers. It also supports the next generation of client management through the use of
PROActive technology in conjunction with Intel's next generation Gigabit Ethernet
controller. Functions and capabilities include:
Advanced Configuration and Power Interface, Version 2.0 (ACPI)
•
Power SMBus
•
I
•
2
C
SST/PECI for Speed Control
•
SPI Flash BIOS
•
Low Pin Count (LPC) Interface
•
Note: For more information on the ICH9, please refer to Intel's web site at
www.intel.com.