Supero SuperServer 5013C-i, Руководство пользователя

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UPER
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ERVER 5013C-T/5013C-i User's Manual
1-2 Motherboard Features
At the heart of the SuperServer 5013C-T/5013C-i lies the P4SCE, a single
processor motherboard designed to provide maximum performance. Below
are the main features of the P4SCE.
Chipset Overview
The P4SCE is based on Intel’s E7210 chipset. See Figure 1-1 for a block
diagram of the chipset. The E7210 chipset is made up of two main compo-
nents:
The Memory Controller Hub (MCH)
The I/O Controller Hub (ICH5R)
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, memory interface, ICH5R inter-
face, CSA interface and AGP interface. It contains advanced power man-
agement logic and supports dual-channel (interleaved) DDR memory, provid-
ing bandwidth of up to 6.4 GB/s using DDR-400 SDRAM. The AGP interface
supports 8x data transfers and operates at a peak bandwidth of 2.1 GB/s.
The CSA (Communications Streaming Architecture) interface connects the
MCH to a Gigabit Ethernet controller.
I/O Controller Hub (ICH5R)
The ICH5R I/O controller hub integrates an Ultra ATA 100 controller, two Serial
ATA host controllers, one EHCI host controller and and four UHCI host controllers
to support up to eight external USB 2.0 ports. The ICH5R also integrates an LPC
interface controller, a flash BIOS interface controller, a PCI interface controller,
an AC ’97 digital controller, an integrated LAN controller, an ASF controller and
a hub interface for communication with the MCH. The ICH5R provides data
buffering and interface arbitration to offer efficient communication between
system interfaces operate and to provide high bandwidth for peak performance.
The ICH5R supports Serial ATA with Intel® RAID Technology.