Supermicro PIIISEA, Руководство пользователя

Страница: 60 / 88

BIOS User's Manual
4-10
BIOS
DRAM Cycle Time (SCLKS)
The settings for this option are
Fast
or
Slow
.
CAS# Latency (SCLKS)
This option regulates the column address strobe. The settings for this
option are 2 SCLKs or 3 SCLKs .
RAS to CAS Delay (SCLKS)
This option specifies the length of the delay inserted between the RAS (Row
Address Strobe) and CAS (Column Address Strobe) signals of the DRAM
system memory access cycle. The settings are Auto (AMIBIOS automati-
cally determines the optimal delay),
2 SCLKs
or
3 SCLKs
.
SDRAM RAS# Precharge (SCLKS)
This option specifies the length of the RAS precharge part of the DRAM
system memory access cycle when Synchronous DRAM system memory is
installed in the computer. The settings are Auto (AMIBIOS automatically
determines the optimal delay), 2 SCLKs or 3 SCLKs .
Display Cache Window Size
This option specifies the cache size to be used for the display data. The
settings are 32MB and 64MB .
CPU Speed at 133/100/66 MHz
This allows you to change the CPU speed (unless "Auto" has been
selected with JP11 and 12.) The "Reserved" setting has no effect. The
others list the CPU speeds: the paired numbers are the CPU speed at 133
or 100 and 66 MHz FSB. The first number is the resulting CPU core/bus
ratio. (The 133 MHz and 100/66 MHz settings are shown separately.)
Initialize Display Cache Memory
The onboard video included in your motherboard includes a 4 MB onboard
display cache (not available with the 370SWM). When set to
Enable
, this
cache will be utilized and the following five settings can be accessed. When
Disabled
, the cache will not be used and the following five settings are also
disabled.
Paging Mode Control
The settings for this option are Close and Open .
RAS-to-CAS
This option specifies the interval between Refresh signals to DRAM
system memory. The settings for this option are Default and Override .