sunair RT-9000C, Руководство по эксплуатации и обслуживанию

Страница: 335 / 393

RT-9000C Hardware Supplement
Document No. 8121000602
Revision A (19 Mar 2007)
8-11
RT-9000 C
U106 and U104 amplify the signal output from the active VCO. The signal is then routed to power divider
T101, which sends half the applied power to PLL Control U101 as a feedback signal. The other half of the
signal power is sent to coaxial connector P3 located on the card edge as the First Local Oscillator output.
The feedback signal from the power divider enters PLL Control U101-pin 4 where it is internally routed to a
programmable frequency divider. The division ratio is directly related to the radio’s selected operating
frequency and is such that the divider output is approximately 100 kHz. The 10.7 MHz Reference signal
enters U101-pin 1 where it is internally routed to another frequency divider. This divider has a fixed division
ratio of 107 to produce an internal 100 kHz reference signal. An internal frequency/phase detector in U101
compares these two 100 kHz signals and determines if the VCO frequency is correct. The detector error
signal output appears on U101-pins 14 & 15 depending on whether the VCO frequency is above or below its
nominal frequency.
If the frequency is incorrect, the error output from U101 will cause Charge Pump U103 to change the voltage
applied to the VCO varactor diodes. This causes the VCO to change its frequency output until it is correct.
U101 also produces lock-detect status signals the BITE circuit (Built-In-Test-Equipment) uses to determine
Fault status.
Second Local Oscillator Signal Generation
The Second Local Oscillator (LO2) is similar to the First Local Oscillator except it operates at a fixed
frequency of 47.85 MHz. The single frequency-operating mode of LO2 requires only one voltage-controlled
oscillator (VCO). This VCO circuit is virtually identical to those used for the LO1 function.
U308 and U307 amplify the VCO signal output. The signal is then routed to power divider T301, which sends
half the applied power to PLL Control U301 as a feedback signal. The other signal half is sent to mixer X301
where the signal can be gated on and off by a control signal from noise blanker multivibrator U306. The
resulting signal is then routed to coaxial connector P4 located on the card edge as the Second Local
Oscillator output.
Feedback signal processing and use is the same as for the LO1 circuit except with the following differences.
PLL Control U301 controls LO2 but instead divides the feedback signal by a fixed ratio of 957 to produce
approximately 50 kHz. U301 accepts buffered 5 MHz Reference signal from the earlier reference section but
divides it by a fixed ratio of 100 to produce an internal 50 kHz reference signal. These signals are compared
and the resulting error signal is passed to charge pump U303 and causes it to lock the VCO at 47.850 MHz.
U301 also produces lock-detect status signals for BITE circuit Fault status determination.
Third Local Oscillator / BFO Signal Generation
The Third Local Oscillator (or BFO) signal is generated by U202 and U201. U202 accepts buffered 5 MHz
Reference signal from the earlier reference section, divides it by two, and produces the BFO CLOCK signal.
U201 further divides the 2.5 MHz BFO CLOCK signal down to 455 kHz and where it passes to Q202. The
signal is amplified by Q202 and sent to a low pass filter. It finally is band-pass filtered by FL201 and routed to
card edge connector P1-pin 2 as BFO OUT. U205-E provides a buffered sample of the BFO output for BITE
status monitoring.
Synthesizer Control
This synthesizer design replaces an earlier design and must be a form, fit, and function equivalent.
Accordingly, this newer design must be fully compatible with all earlier radio CPU assemblies. To achieve this
interchangeability this synthesizer design must translate all original commands to those required for this new
design. This task is handled by micro-controller U401. U401 is an 80C51 micro-controller family variation and
has internal program and data memory. A buffered output of the 25 MHz Reference signal is supplied to
U403, which divides it by two and sends to U401 as its clock signal.