sunair RT-9000C, Руководство по эксплуатации и обслуживанию

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RT-9000C Hardware Supplement
Document No. 8128000602
Revision A (19 Mar 2007)
8-10
RT-9000 C
8.3.1 Frequency Synthesizer 1A2A2
8.3.1.1 Description
This section describes a Direct Digital Synthesis (DDS) Frequency Synthesizer design, which replaces an
earlier “all Phase-Locked-Loop” design. This replacement design was created in response to component part
obsolescence and availability issues. The DDS synthesizer design has been in production since
approximately 2001. This replacement assembly and its creation was not related to the RT-9000C product.
This DDS synthesizer was designed to be fully backward compatible with all Sunair 9000-series radios. No
adjustments or alignment whatsoever is required for proper operation. Both synthesizers retain the same
Sunair Part Number (8076060095, in this case) but are distinguished from each other by their Revision Level.
The earlier now-obsolete assembly was Revision A, whereas the new DDS assembly is now Revision B or
higher.
8.3.1.2 Theory of Operation
5 MHz Reference Signal Input
A 5 MHz square wave input reference signal enters the 1A2A2 Frequency Synthesizer at card edge
connector P1-pin 22 from the radio’s frequency standard. This signal is band-pass filtered and amplified. This
reference signal determines the ultimate accuracy and stability of all synthesizer output frequencies. Buffered
outputs of this signal are sent to the 25 MHz Generator, the Second Local Oscillator PLL Controller U301,
and the BITE CLOCK input of U202.
25 MHz Signal Generation
Selecting the fifth harmonic of the 5 MHz square wave reference signal using filtering techniques generates a
25 MHz signal. A filter network composed of passive components is inserted between U402-C & D and U409.
A similar network is also present between U409 and U406-A to finish the required filtering. Normal operation
of these filters causes the 25 MHz signal output to be a sinusoidal waveform. U406-A converts the sine wave
output back to a square wave waveform.
First Local Oscillator Reference Generation
Using the 25 MHz signal, U1 generates a reference frequency used primarily for the First Local Oscillator
generation (LO1). This reference frequency is approximately 10.7 MHz. U1 generates the 10.7 MHz signal by
dividing down the 25 MHz signal input at U1-pin 9.
Besides the desired 10.7 MHz signal, U1 also creates undesired signals at other frequencies. The output
from U1 passes through a low-pass filter composed of inductors L1, L2, and L3 and their related parts. The
signal is finally band-pass filtered by filters FL1A and FL1B. The filtered 10.7 MHz reference frequency is
amplified by U2 and U3. The 10.7 MHz Reference signal is then routed to First Local Oscillator PLL Control
U101.
First Local Oscillator Signal Generation
The First Local Oscillator is a phase-locked loop (PLL) design and contains four (4) voltage-controlled
oscillators (VCOs). Each VCO is built around a U310 JFET transistor with appropriate parts for the frequency
output segment it covers. Only one VCO is active at any given time. The radio enables the proper VCO using
the VCO SELECT lines at card edge connector P1-pins 20, 17, 19, or 16. VCO selection is based on the
radio’s selected operating frequency.