STM32F42xx and STM32F43xx silicon limitations
STM32F42xx and STM32F43xx
DocID023833 Rev 5
2.8.4 Corruption
of
data read from the FMC
Description
When the FMC is used as stack, heap or variable data, an interrupt occurring during a CPU
read access to the FMC may results in read data corruption or hard fault exception. This
problem does not occur when read accesses are performed by another master or when
FMC accesses are done when the interrupts are disabled.
Workaround
Two workarounds can be applied:
•
Do not use the FMC as stack or heap, and make sure CPU read accesses to the FMC
are performed while interrupts are disabled
•
Use only DMAs to perform read accesses to the FMC.
This limitation is fixed in silicon revision Y.
2.8.5
Interruption of CPU read burst access to an end of SDRAM row
Description
If an interrupt occurs during an CPU AHB burst read access to an end of SDRAM row, it
may result in wrong data read from the next row if all the conditions below are met:
•
The SDRAM data bus is 16-bit or 8-bit wide. 32-bit SDRAM mode is not affected.
•
RBURST bit is reset in the FMC_SDCR1 register (read FIFO disabled).
•
An interrupt occurs while CPU is performing an AHB incrementing bursts read access
of unspecified length (using LDM = Load Multiple instruction).
•
The address of the burst operation includes the end of an SDRAM row.
Workaround
Enable the read FIFO by setting the RBURST bit in the FMC_SDCR1 register.
2.8.6
FMC NOR/PSRAM controller: asynchronous read access on bank 2 to 4
returns wrong data when bank 1 is in synchronous mode
(BURSTEN bit is set)
Description
If an interrupt occurs during a CPU AHB read access to one NOR/PSRAM bank (bank2 to 4)
which is enabled in asynchronous mode, while bank 1 of the NOR/PSRAM controller is
configured in synchronous read mode (BURSTEN bit set to ‘1’), then the FMC NOR/PSRAM
controller returns wrong data.
This limitation does not occur when using the DMA or when only bank1 is used in
synchronous mode.
Workaround
If multiple banks are enabled in mixed asynchronous and synchronous modes, use any
NOR/PSRAM bank for synchronous read accesses, except for bank 1. As a consequence
the continuous clock feature is not available in asynchronous mode.
