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STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx
10/36 DocID023833 Rev 5
2.1 System limitations
2.1.1 Debugging Stop mode and system tick timer
Description
If the system tick timer interrupt is enabled during the Stop mode debug (DBG_STOP bit set
in the DBGMCU_CR register), it will wake up the system from Stop mode.
Workaround
To debug the Stop mode, disable the system tick timer interrupt.
2.1.2 Debugging Stop mode with WFE entry
Description
When the Stop debug mode is enabled (DBG_STOP bit set in the DBGMCU_CR register),
this allows software debugging during Stop mode.
However, if the application software uses the WFE instruction to enter Stop mode, after
wakeup some instructions could be missed if the WFE is followed by sequential instructions.
This affects only Stop debug mode with WFE entry.
Workaround
To debug Stop mode with WFE entry, the WFE instruction must be inside a dedicated
function with 1 instruction (NOP) between the execution of the WFE and the Bx LR.
Example:
__asm void _WFE(void) {
WFE
Section 2.9: SDIO
peripheral limitations
Section 2.9.1: SDIO HW flow control N N
Section 2.9.2: Wrong CCRCFAIL status after a response
without CRC is received
A A
Section 2.9.3: Data corruption in SDIO clock dephasing
(NEGEDGE) mode
N N
Section 2.9.4: CE-ATA multiple write command and card
busy signal management
A A
Section 2.9.5: No underrun detection with wrong data
transmission
A A
Section 2.10: ADC
peripheral limitations Section 2.10.1: ADC sequencer modification during
conversion
A A
Section 2.11: DAC
peripheral limitations
Section 2.11.1: DMA underrun flag management A A
Section 2.11.2: DMA request not automatically cleared by
DMAEN=0
A A
Table 4. Summary of silicon limitations (continued)
Links to silicon limitations Revision A Revision Y