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STM32F42xx and STM32F43xx
STM32F42xx and STM32F43xx silicon limitations
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Section 2.5: USART
peripheral limitations
Section 2.5.1: Idle frame is not detected if receiver clock
speed is deviated
N
N
A
A
N
N
Section 2.5.4: Break frame is transmitted regardless of
nCTS input line status
N
N
Section 2.5.5: nRTS signal abnormally driven low after a
protocol violation
A
A
Section 2.6: OTG_FS
peripheral limitations
Section 2.6.1: Data in RxFIFO is overwritten when all
channels are disabled simultaneously
A
A
A
A
Section 2.6.3: Host channel-halted interrupt not generated
when the channel is disabled
A
A
Section 2.6.4: Error in software-read OTG_FS_DCFG
register values
A
A
Section 2.7: Ethernet
peripheral limitations
A
A
Section 2.7.2: The Ethernet MAC processes invalid
extension headers in the received IPv6 frames
N
N
A
A
Section 2.7.4: Transmit frame data corruption
A
A
A
A
Section 2.8: FMC peripheral
limitation
Section 2.8.1: Dummy read cycles inserted when reading
synchronous memories
N
N
Section 2.8.2: FMC synchronous mode and NWAIT signal
disabled
A
A
Section 2.8.3: Read access to a non-initialized
FMC_SDRAM bank
P
P
Section 2.8.4: Corruption of data read from the FMC
A
-
Section 2.8.5: Interruption of CPU read burst access to an
end of SDRAM row
A
A
A
A
Section 2.8.7: FMC dynamic and static banks switching
A
A
Table 4. Summary of silicon limitations (continued)
Links to silicon limitations
Revision A Revision Y