STM32F42xx and STM32F43xx silicon limitations
STM32F42xx and STM32F43xx
DocID023833 Rev 5
2.1.5
MPU attribute to RTC and IWDG registers could be managed
incorrectly
Description
If the MPU is used and the non bufferable attribute is set to the RTC or IWDG memory map
region, the CPU access to the RTC or IWDG registers could be treated as bufferable,
provided that there is no APB prescaler configured (AHB/APB prescaler is equal to 1).
Workaround
If the non bufferable attribute is required for these registers, the software could perform a
read after the write to guaranty the completion of the write access.
2.1.6
Delay after an RCC peripheral clock enabling
Description
A delay between an RCC peripheral clock enable and the effective peripheral enabling
should be taken into account in order to manage the peripheral read/write to registers.
This delay depends on the peripheral’s mapping:
•
If the peripheral is mapped on AHB: the delay should be equal to 2 AHB cycles.
•
If the peripheral is mapped on APB: the delay should be equal to 1 + (AHB/APB
prescaler) cycles.
Workarounds
1.
Use the DSB instruction to stall the Cortex-M CPU pipeline until the instruction is
completed.
2.
Insert “n” NOPs between the RCC enable bit write and the peripheral register writes
(n = 2 for AHB peripherals, n = 1 + AHB/APB prescaler in case of APB peripherals).
2.1.7
Internal noise impacting the ADC accuracy
Description
An internal noise generated on V
DD
supplies and propagated internally may impact the ADC
accuracy.
This noise is always active whatever the power mode of the MCU (RUN or Sleep).
Workarounds
To adapt the accuracy level to the application requirements, set one of the following options:
•
Option1
Set the ADCDC1 bit in the PWR_CR register.
•
Option2
Set the corresponding ADCxDC2 bit in the SYSCFG_PMC register.
Only one option can be set at a time.
For more details on option 1 and option2 mechanisms, refer to AN4073.