STMicroelectronics STM32F427, Руководство пользователя, Страница: 35 / 36

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STM32F42xx and STM32F43xx Revision history
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Revision history
Table 6. Document revision history
Date Revision Changes
11-Feb-2013 1 Initial release.
25-Feb-2013 2
Document converted to new template.
Added Section 2.8.4: Corruption of data read from the FMC
26-Apr-2013 3
Added Silicon revision Y.
Removed the reference to ‘Cortex-M4F’ in the whole document.
Updated Section 2.8.1: Dummy read cycles inserted when reading
synchronous memories .
Added Section 2.1.3: Wakeup sequence from Standby mode when
using more than one wakeup source , Section 2.7.5: Successive write
operations to the same register might not be fully taken into account
and Section 2.8.3: FSMC NOR Flash/PSRAM controller
asynchronous access on bank 2 to 4 when bank 1 is in synchronous
mode (CBURSTRW bit is set)
.
Removed limitation 2.10.3 SDIO clock divider BYPASS mode may
not work properly. Updated
Section 2.9.5: No underrun detection
with wrong data transmission .
19-Sep-2013 4
Added STM32F429xx and STM32F439xx devices.
Removed FSMC limitations.
Added Section 2.3.5: Both SDA and SCL maximum rise time (tr)
violated when VDD_I2C bus higher than ((VDD+0.3) / 0.7) V .
Updated Section 2.8.5: Interruption of CPU read burst access to an
end of SDRAM row .
Added Section 2.8.1: Dummy read cycles inserted when reading
synchronous memories , Section 2.8.2: FMC synchronous mode and
NWAIT signal disabled , Section 2.8.3: Read access to a non-
initialized FMC_SDRAM bank , Section 2.8.4: Corruption of data read
from the FMC , Section 2.8.5: Interruption of CPU read burst access
to an end of SDRAM row , Section 2.8.6: FMC NOR/PSRAM
controller: asynchronous read access on bank 2 to 4 returns wrong
data when bank 1 is in synchronous mode (BURSTEN bit is set)
and
Section 2.8.7: FMC dynamic and static banks switching .
Added Figure 1: TFBGA216 top package view , Figure 2: WLCSP143
top package view , and Figure 3: LQFP208 top package view .
23-Sep-2013 5
Updated workaround in Section 2.8.6: FMC NOR/PSRAM controller:
asynchronous read access on bank 2 to 4 returns wrong data when
bank 1 is in synchronous mode (BURSTEN bit is set)
.