Spectrum M3i.4830, Руководство по оборудованию

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Introduction Hardware information
(c) Spectrum GmbH 13
Technical Data
Analog Inputs
Trigger
Clock
Resolution 16 bit
Input Type Single-ended
Programmable Input Offset not available
ADC Differential non linearity (DNL) ADC only
≤
1.0 LSB
ADC Integral non linearity (INL) ADC only
≤
4.0 LSB
Channel selection software programmable 1 or 2 channels (maximum is model dependent)
Bandwidth filter 4830, 4831 activate by software 10 MHz bandwidth with 3rd order Butterworth filtering
Bandwidth filter 4840, 4841, 4860, 4861 activate by software 20 MHz bandwidth with 3rd order Butterworth filtering
Input Path Types software programmable
50
Ω
(HF) Path
Buffered (high impedance) Path
Analog Input impedance software programmable
50
Ω
1 M
Ω
|| 25 pF or 50
Ω
Input Ranges software programmable ±500 mV, ±1 V, ±2.5 V, ±5 V ±200 mV, ±500 mV, ±1 V, ±2 V, ±5 V, ±10 V
Input Coupling software programmable AC/DC AC/DC
Offset error (full speed) after warm-up and calibration
≤
0.1%
≤
0.1%
Gain error (full speed) after warm-up and calibration
≤
1.0%
≤
0.1%
Over voltage protection range
≤
±1V 2 Vrms
±5 V (1 M
Ω),
5 Vrms (50
Ω
)
Over voltage protection range
≥
±2V 6 Vrms
±30 V (1 M
Ω),
5 Vrms (50
Ω
)
Max DC voltage if AC coupling active ±30 V ±30 V
Relative input stage delay 0 ns 3.8 ns
Crosstalk 1 MHz sine signal input range ±1 V not available
≤
-100 dB
Crosstalk 20 MHz sine signal input range ±1 V not available
≤
-100 dB
Crosstalk 1 MHz sine signal input range ±5 V
≤
-110 dB
≤
-92 dB
Crosstalk 20 MHz sine signal input range ±5 V
≤
-102 dB
≤
-92 dB
Available trigger modes software programmable Channel Trigger, Ext0 (Analog), Ext1 (TT), Software, Window, Re-Arm, Or/And, Delay
Trigger level resolution software programmable 10 bits
Trigger edge software programmable Rising edge, falling edge or both edges
Trigger delay software programmable 0 to (8GSamples - 8) = 8589934584 Samples in steps of 8 samples
Multi, Gate: re-arming time
≤
32 samples (+ programmed pretrigger)
Pretrigger at Multi, ABA, Gate, FIFO software programmable 8 up to [8192 Samples / number of active channels] in steps of 8
Posttrigger software programmable 8 up to 4 GSamples in steps of 8(defining pretrigger in standard scope mode)
Memory depth software programmable 16 up to [installed memory / number of active channels] samples in steps of 8
Multiple Recording/ABA segment size software programmable 16 up to [installed memory / 2 / active channels] samples in steps of 16
Trigger output delay after trigger input 134 sampling clock cycles
Internal/External trigger accuracy 1 sample
External trigger Ext0 (Trg) Ext1 (X0) + Ext2 (X1)
External trigger impedance software programmable
50
Ω
/1 M
Ω
|| 25 pF 10 k
Ω
to 3.3 V
External trigger coupling software programmable AC or DC fixed DC
Minimum trigger pulse width (DC / AC)
≥
2 samples
≥
2 samples
External trigger bandwidth DC
50
Ω
/1 M
Ω
DC to 200 MHz / 150 MHz DC to 125 MHz
External trigger bandwidth AC
50
Ω
20 kHz to 200 MHz n.a.
External trigger type Window comparator, ±5 V TTL level
External trigger level software programmable 2 levels ±5V in steps of 1 mV fixed: Low:
≤
0.8 V, High:
≥
2.0 V
External trigger maximum voltage
5V rms (50
Ω),
±30V (1 M
Ω)
-0.3 V to +5.5V
External trigger output impedance input only
50
Ω
External trigger output levels input only Low:
≤
0.4 V, High:
≥
2.4 V
External trigger output type input only 3.3 V LVTTL.TTL compatible for high impedance
External trigger output drive strength input only
Capable of driving 50
Ω
loads, ±64 mA output
Clock Modes software programmable internal, external reference clock, sync
Internal clock accuracy
≤
±32 ppm
Internal clock setup granularity 1 Hz (except the clock setup gaps shwon below)
Clock setup range gaps clock not programmable 70 MHz to 72 MHz, 140 MHz to 144 MHz, 281 MHz to 287 MHz
External reference clock range software programmable
≥
10 MHz and
≤
1 GHz (fix at runtime)
External reference clock setup granilarity 1 kHz
External clock input impedance software programmable
50
Ω
fixed
External clock input coupling AC coupling
External clock input edge Rising edge
External clock input to internal ADC clock delay 3.7 ns (8.2 ns if synchronization is used)
External clock input type Single-ended, sine wave or square wave
External clock input swing 0.3 V peak-peak up to 3.0 V peak-peak
External clock input max DC voltage ±30 V (with max 3.0 V difference between low and high level)
External clock input duty cycke requirement 40% to 60%
External clock output type Single-ended, 3.3V LVPECL
External clock output coupling AC coupling
ABA mode clock divider for slow clock software programmable 8 up to [128k - 8] in steps of 8