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M3i.48xx / M3i.48xx-exp Manual
Details on the different clock modes
Clock generation
External clock (reference clock)
The external clock input is fed through a PLL to the clock system. Therefore the input will act as a reference clock input thus allowing to either
use a copy of the external clock or to generate any sampling clock within the allowed range from the reference clock. Please note the limited
setup granularity in comparison to the internal sampling clock generation. Details are found in the technical data section.
Due to the fact that the driver needs to know the external fed in frequency for an exact calculation of the sampling rate you must set the
SPC_REFERENCECLOCK register accordingly as shown in the table below. The driver then automatically sets the PLL to achieve the desired
sampling rate. Please be aware that the PLL has some internal limits and not all desired sampling rates may be reached with every reference
clock.
Example of reference clock:
PLL Locking Error
The external clock signal is routed to a PLL to generate any sampling clock from this external clock. Due to the internal structure of the card
the PLL is even used if a copy of the clock fed in externally is used for sampling (SPC_REFERENCECLOCK = SPC_SAMPLERATE). The PLL needs
a stable and defined external clock with no gaps and no variation in the frequency. The external clock must be present when issuing the start
command. It is not possible to start the card with external clock activated and no external clock available.
When starting the card all settings are written to hardware and the PLL is programmed to generate the desired sampling clock. If there has
been any change to the clock setting the PLL then tries to lock on the external clock signal to generate the sampling clock. This locking will
normally need 10 to 20 ms until the sampling clock is stable. Some clock settings may also need 200 ms to lock the PLL. This waiting time is
automatically added at card start.
However if the PLL can not lock on the external clock either because there is no clock available or it hasn’t sufficient signal levels or the clock
is not stable the driver will return with an error code ERR_CLOCKNOTLOCKED. In that case it is necessary to check the external clock con-
nection. Please see the example below:
Register
Value
Direction
Description
SPC_CLOCKMODE
20200
read/write
Defines the used clock mode
SPC_CM_EXTREFCLOCK
32
Enables internal PLL with external reference for sample clock generation
Register
Value
Direction
Description
SPC_REFERENCECLOCK
20140
read/write
Programs the external reference clock in the range stated in the technical data section.
External sampling rate in Hz as an integer value
You need to set up this register exactly to the frequency of the external fed in clock.
spcm_dwSetParam_i32 (hDrv, SPC_CLOCKMODE, SPC_CM_EXTREFCLOCK); // Set to reference clock mode
spcm_dwSetParam_i32 (hDrv, SPC_REFERENCECLOCK, 10000000); // Reference clock that is fed in is 10 MHz
spcm_dwSetParam_i64 (hDrv, SPC_SAMPLERATE, 65200000); // We want to have 62.5 MHz as sampling rate
// settings done to external clock like shown above.
if (spcm_dwSetParam_i32 (hDrv, SPC_M2CMD, M2CMD_CARD_START | M2CMD_CARD_ENABLETRIGGER) == ERR_CLOCKNOTLOCKED)
{
printf („External clock not locked. Please check connection\n“);
return -1;
}
