1-43
IC
VGN-
S36C/S36GP/S36LP/S36SP/S36TP/S38CP/
S52B/
S62PS/S62PSY/S62S/
S350F/S350FP/
S360/S360P/
S370F
(J/AM
/AO
)
Confidential
Table 2−6. PCI Terminals (Continued)
TERMINAL
I/O
POWER
EXTERNAL
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
OUTPUT
POWER
RAIL
EXTERNAL
COMPONENTS
GNT
R02
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the
PCI7420B device access to the PCI bus after the current data
transaction has completed. GNT may or may not follow a PCI bus
request, depending on the PCI bus parking algorithm.
I
PCII1
−
VCCP
−
IDSEL
V03
Initialization device select. IDSEL selects the PCI7420B device during
configuration space accesses. IDSEL can be connected to 1 of the
upper 24 PCI address lines on the PCI bus.
I
PCII1
−
VCCP
−
IRDY
U06
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK where both IRDY and TRDY are
asserted. Until IRDY and TRDY are both sampled asserted, wait
states are inserted.
I/O
PCII2
PCIO2
VCCP
Pullup resistor
per PCI
specification
PERR
U07
PCI parity error indicator. PERR is driven by a PCI device to indicate
that calculated parity does not match PAR when PERR is enabled
through bit 6 of the command register (PCI offset 04h, see
Section 4.4).
I/O
PCII2
PCIO2
VCCP
Pullup resistor
per PCI
specification
REQ
T01
PCI bus request. REQ is asserted by the PCI7420B device to request
access to the PCI bus as an initiator.
O
−
PCIO2
VCCP
−
SERR
V07
PCI system error. SERR is an output that is pulsed from the PCI7420B
device when enabled through bit 8 of the command register (PCI offset
04h, see Section 4.4) indicating a system error has occurred. The
PCI7420B device need not be the target of the PCI cycle to assert this
signal. When SERR is enabled in the command register, this signal
also pulses, indicating that an address parity error has occurred on a
CardBus interface.
O
−
PCIO2
VCCP
Pullup resistor
per PCI
specification
STOP
W06
PCI cycle stop signal. STOP is driven by a PCI target to request the
initiator to stop the current PCI bus transaction. STOP is used for
target disconnects and is commonly asserted by target devices that do
not support burst data transfers.
I/O
PCII2
PCIO2
VCCP
Pullup resistor
per PCI
specification
TRDY
V06
PCI target ready. TRDY indicates the ability of the primary bus target
to complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK when both IRDY and TRDY are
asserted. Until both IRDY and TRDY are asserted, wait states are
inserted.
I/O
PCII2
PCIO2
VCCP
Pullup resistor
per PCI
specification
Table 2−7. Multifunction and Miscellaneous Terminals
The power rail designation is not applicable for the multifunction and miscellaneous terminals.
TERMINAL
I/O
PU/
EXTERNAL
PIN STRAPPING
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
OUTPUT
PU/
PD
EXTERNAL
COMPONENTS
PIN STRAPPING
(IF UNUSED)
GRST
N05
Global reset. When the global reset is asserted, the
GRST signal causes the PCI7420B device to place all
output buffers in a high-impedance state and reset all
internal registers. When GRST is asserted, the device
is completely in its default state. For systems that
require wake-up from D3, GRST is normally asserted
only during initial boot. PRST must be asserted
following initial boot so that PME context is retained
when transitioning from D3 to D0. For systems that do
not require wake-up from D3, GRST must be tied to
PRST. When the SUSPEND mode is enabled, the
device is protected from the GRST, and the internal
registers are preserved. All outputs are placed in a
high-impedance state, but the contents of the registers
are preserved.
I
PCII3
−
−
PowerOn reset or
tied to PRST
NA
CLK48
L02
48 MHz clock terminal
I
LVC1
−
−
48-MHz clock
source
NA
MFUNC0
M03
Multifunction terminal 0. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
MFUNC1
L06
Multifunction terminal 1. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
MFUNC2
N01
Multifunction terminal 2. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
MFUNC3
N02
Multifunction terminal 3. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
MFUNC4
N03
Multifunction terminal 4. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
MFUNC5
M05
Multifunction terminal 5. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
MFUNC6
P01
Multifunction terminal 6. See Section 4.36,
Multifunction
Routing Status Register
, for configuration details.
I/O
PCII2
PCIO2
−
−
Pulled up through
10-k
Ω
to 47-k
Ω
resistor
PHY_TEST
_MA
R17
PHY test pin. Not for customer use. It must be pulled
high.
I
LVCI1
−
−
1-k
Ω
to 4.7-k
Ω
pullup resistor
NA
RI_OUT/
PME
R03
Ring indicate out and power management event output.
This terminal provides an output for ring-indicate or
PME signals.
O
−
LVCO2
−
Pullup resistor
per PCI
Specification
NA
RSVD
H05,
J05,
J06,
K01,
K02,
K03
Reserved. These terminals have no connection
anywhere within the package.
−
−
−
−
−
Float
SCL
K07
Serial clock. At the deassertion of GRST, the SCL
signal is sampled to determine if a two-wire serial ROM
is present. If the serial ROM is detected, then this
terminal provides the serial clock signaling and is
implemented as open-drain. For normal operation (a
ROM is implemented in the design), this terminal must
be pulled high to the ROM VDD with a resistor.
Otherwise, it must be pulled low to ground.
I/O
TTLI1
TTLO1
−
Pullup resistor
per I2C
specification
(value depends
on EEPROM,
typically 2.7 k
Ω
)
Tie to GND if not
using EEPROM
Table 2−7. Multifunction and Miscellaneous Terminals (Continued)
TERMINAL
I/O
PU/
EXTERNAL
PIN STRAPPING
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
OUTPUT
PU/
PD
EXTERNAL
COMPONENTS
PIN STRAPPING
(IF UNUSED)
SDA
L03
Serial data. This terminal provides the serial data
signaling and is implemented as open-drain. For normal
operation (a ROM is implemented in the design), this
terminal must be pulled high to the ROM VDD.
Otherwise, it must be pulled low to ground.
I/O
TTLI2
TTLO2
−
Pullup resistor
per I2C
specification
(value depends
on EEPROM)
Tie to GND if not
using EEPROM
SPKROUT
L07
Speaker output. SPKROUT is the output to the host
system that can carry SPKR or CAUDIO through the
PCI7420B device from the PC Card interface.
SPKROUT is driven as the exclusive-OR combination of
card SPKR//CAUDIO inputs.
O
−
TTLO1
−
10-k
Ω
to 47-k
Ω
pulldown resistor
10-k
Ω
to 47-k
Ω
pulldown resistor
SUSPEND
P02
Suspend. SUSPEND protects the internal registers from
clearing when the GRST or PRST signal is asserted.
See Section 3.9.6,
Suspend Mode
, for details.
I
PCII3
−
−
10-k
Ω
to 47-k
Ω
pullup resistor
10-k
Ω
to 47-k
Ω
pullup resistor
TEST0
R19
Terminal TEST0 is used for factory test of the device
and must be connected to ground for normal operation.
I/O
LVC1
−
PD1
−
Tie to GND
Table 2−8. 16-Bit PC Card Terminals
External components are not applicable for the 16-bit PC Card terminals. If any 16-bit PC Card terminal is unused,
then the terminal may be left floating.
SKT A TERMINAL
SKT B TERMINAL
I/O
POWER
NAME
NO.
NAME
NO.
DESCRIPTION
I/O
TYPE
POWER
RAIL
A_A25
A_A24
A_A23
A_A22
A_A21
A_A20
A_A19
A_A18
A_A17
A_A16
A_A15
A_A14
A_A13
A_A12
A_A11
A_A10
A_A9
A_A8
A_A7
A_A6
A_A5
A_A4
A_A3
A_A2
A_A1
A_A0
A06
B07
E08
C08
A08
G09
B09
E10
B10
B08
F09
C09
A09
A07
B11
C12
F10
C10
C07
B06
A05
B05
C05
E06
A03
B03
B_A25
B_A24
B_A23
B_A22
B_A21
B_A20
B_A19
B_A18
B_A17
B_A16
B_A15
B_A14
B_A13
B_A12
B_A11
B_A10
B_A9
B_A8
B_A7
B_A6
B_A5
B_A4
B_A3
B_A2
B_A1
B_A0
H14
H15
G18
H13
H18
J15
J17
K15
K18
H17
G19
J13
J18
G17
L18
M18
K14
K17
F19
F17
G15
E18
F15
C19
D17
F14
PC Card Address Terminals. 16-bit PC Card address lines. A25 is the most significant
bit.
I/O
VCCA/
VCCB
A_D15
A_D14
A_D13
A_D12
A_D11
A_D10
A_D9
A_D8
A_D7
A_D6
A_D5
A_D4
A_D3
A_D2
A_D1
A_D0
A12
A13
B13
B14
C14
E03
D01
D03
E12
C13
A14
F12
A15
F05
D02
E05
B_D15
B_D14
B_D13
B_D12
B_D11
B_D10
B_D9
B_D8
B_D7
B_D6
B_D5
B_D4
B_D3
B_D2
B_D1
B_D0
M19
N19
N17
M14
P18
E13
A16
B16
L13
N18
M15
P19
P17
C15
E14
A17
PC Card Data. 16-bit PC Card data lines. D15 is the most significant bit.
I/O
VCCA/
VCCB
A_BVD1
(STSCHG/Ri)
C03
B_BVD1
(STSCHG/RI)
A18
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include
batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on
a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When
BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When
BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card
is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register
,
for enable bits. See Section 5.5,
ExCA Card Status-Change Register
, and
Section 5.2,
ExCA Interface Status Register
, for the status bits for this signal.
Status Change. STSCHG is used to alert the system to a change in the READY, write
protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
I
VCCA/
VCCB
A_BVD2
(SPKR)
B01
B_BVD2
(SPKR)
C17
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include
batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on
a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When
BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When
BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card
is lost. See Section 5.6,
ExCA Card Status-Change Interrupt Configuration Register
,
for enable bits. See Section 5.5,
ExCA Card Status-Change Register
, and
Section 5.2,
ExCA Interface Status Register
, for the status bits for this signal.
Speaker. SPKR is an optional binary audio signal available only when the card and
socket have been configured for the 16-bit I/O interface. The audio signals from cards
A and B are combined by the PCI7420B device and are output on SPKROUT.
I
VCCA/
VCCB
NOTE: The 16-bit PC card terminals are multiplexed with the CardBus PC card terminals. The input and output buffer information is available in
the CardBus PC card terminals table.
Table 2−8. 16-Bit PC Card Terminals (Continued)
SKT A TERMINAL
SKT B TERMINAL
I/O
POWER
NAME
NO.
NAME
NO.
DESCRIPTION
I/O
TYPE
POWER
RAIL
A_CD1
A_CD2
B15
C01
B_CD1
B_CD2
N15
C16
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the
PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For
signal status, see Section 5.2,
ExCA Interface Status Register
.
I
−
A_CE1
A_CE2
B12
E11
B_CE1
B_CE2
M17
L15
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered
address bytes. CE1 enables even-numbered address bytes, and CE2 enables
odd-numbered address bytes.
O
VCCA/
VCCB
A_INPACK
F06
B_INPACK
E17
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O
read cycle at the current address.
I
VCCA/
VCCB
A_IORD
C11
B_IORD
L17
I/O read. IORD is asserted by the PCI7420B device to enable 16-bit I/O PC Card data
output during host I/O read cycles.
O
VCCA/
VCCB
A_IOWR
G10
B_IOWR
K13
I/O write. IOWR is driven low by the PCI7420B device to strobe write data into 16-bit I/O
PC cards during host I/O write cycles.
O
VCCA/
VCCB
A_OE
A11
B_OE
L19
Output enable. OE is driven low by the PCI7420B to enable 16-bit memory PC Card
data output during host memory read cycles.
O
VCCA/
VCCB
A_READY
(IREQ)
A02
B_READY
(IREQ)
B19
Ready. The ready function is provided when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write
command. READY is driven high when the 16-bit memory PC Card is ready to accept a
new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a
device on the 16-bit I/O PC Card requires service by the host software. IREQ is high
(deasserted) when no interrupt is requested.
I
VCCA/
VCCB
A_REG
B04
B_REG
D18
Attribute memory select. REG remains high for all common memory accesses. When
REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O
space (IORD or IOWR active). Attribute memory is a separately accessed section of
card memory and is generally used to record card capacity and other configuration and
attribute information.
O
VCCA/
VCCB
A_RESET
C06
B_RESET
E19
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
O
VCCA/
VCCB
A_VS1
A_VS2
C04
E07
B_VS1
B_VS2
C18
F18
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each
other, determine the operating voltage of the PC Card.
I/O
VCCA/
VCCB
A_WAIT
B02
B_WAIT
B18
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the
memory or I/O cycle in progress.
I
VCCA/
VCCB
A_WE
E09
B_WE
H19
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE
is also used for memory PC Cards that employ programmable memory technologies.
O
VCCA/
VCCB
A_WP
(IOIS16)
C02
B_WP
(IOIS16)
B17
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the
write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the
16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC
Card when the address on the bus corresponds to an address to which the 16-bit PC
Card responds, and the I/O port that is addressed is capable of 16-bit accesses.
I
VCCA/
VCCB
NOTE: The 16-bit PC card terminals are multiplexed with the CardBus PC card terminals. The input and output buffer information is available in
the CardBus PC card terminals table.
