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69
HCD-CP500K/CP500MD
• IC1001 M30805MG-205GP SYSTEM CONTROL (DIGITAL BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
I/O
—
—
—
—
—
—
—
O
O
O
O
I
O
O
I
—
O
O
I
O
—
I
—
I
I
I
I
—
O
I
—
I
—
I
O
I/O
I/O
O
—
I
—
O
I
O
I
O
O
I
I
O
I
Pin Name
—
—
LVLI
LVL0
(TXD3)
(RXD3)
(CLK3)
MUTE
DARST
SLICERSEL
LD-LOW
LDIN
LDOUT
MOD
BYTE
CNVSS
X-CIN
X-COUT
RESET
XOUT
VSS0
XIN
VCC0
NMI
DQSY
P.DOWN
SQSY
NC
LDON
LIMIT-IN
C2-PWM-B
XINIT
—
XELT
WR PWR
IIC CLK
IIC DATA
SWDT
VCC1
SRDT
VSS1
SCLK
REC-SW
CLIP DTO
CLIPDTI
CLIP CLK
DIG-RST
SENS
PLAY-SW
XLAT
OUT-SW
Description
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Line out muting output L: Muting
Reset signal output to the D/A converter L: Active
IEC958 input select signal output to the D/A converter L: CD H: MD
Loading motor voltage control output L: High voltage H: Low voltage
Loading motor control input H: IN
Loading motor control output H: OUT
Laser modulation switching signal output L: OFF H: ON
Data bus changed input (Connected to ground)
Ground
Sub clock input (32.768kHz) (Not used)
Sub clock output (32.768kHz) (Not used)
System rest input L : ON
Main clock output (10MHz)
Ground
Main clock input (10MHz)
Power supply (+3.3V)
Fixed at H (Pull-up)
Digital in sync input (Record system)
Power down detection input L: Power down
ADIP (MO) sync or subcode Q (PIT) sync input from CXD2662R (Playback system)
Not used
Laser ON/OFF control output H: Laser ON
Detection input from the limit switch L: Sled limit-In H: Sled limit-Out
Not used
Interrupt status input from CXD2662R
Not used
XELT input from DSP IC
Write power ON/OFF output L: OFF H: ON
IIC serial clock input/output
IIC serial data input/output
Writing data signal output to the serial bus
Power supply (+3.3V)
Reading data signal input from the serial bus
Ground
Clock signal output to the serial bus
Detection signal input from the recording position detection switch L: REC
CLIP serial data output
CLIP serial data input
CLIP serial clock output (Not used)
Digital rest signal output to the CXD2662R and motor driver L: Reset
Internal status (SENSE) input from the CXD2662R
Detection signal input from the playback position detection switch L: PLAY
Latch signal output to DSP IC
Detection signal input from the loading out detection switch
Содержание HCD-CP500K
Страница 7: ...7 HCD CP500K CP500MD SERVICE POSITION OF THE TAPE MECHANISM DECK Tape mechanism deck CN301 CN303 ...
Страница 39: ...39 HCD CP500K CP500MD MEMO ...
Страница 47: ...HCD CP500K CP500MD 47 47 7 4 SCHEMATIC DIAGRAM CD BOARD Page 52 ...
Страница 49: ...HCD CP500K CP500MD 49 49 7 6 SCHEMATIC DIAGRAM BD BOARD 1 2 Page 50 Page 50 Page 50 ...
Страница 50: ...HCD CP500K CP500MD 50 50 7 7 SCHEMATIC DIAGRAM BD BOARD 2 2 Page 49 Page 49 Page 49 Page 57 Page 57 ...
Страница 55: ...HCD CP500K CP500MD 55 55 7 12 SCHEMATIC DIAGRAM TC BOARD IC B D Page 52 ...
Страница 57: ...HCD CP500K CP500MD 57 57 7 14 SCHEMATIC DIAGRAM DIGITAL BOARD IC B D IC B D IC B D Page 50 Page 50 Page 52 ...
Страница 59: ...HCD CP500K CP500MD 59 59 7 16 SCHEMATIC DIAGRAM CONTROL SECTION Page 53 Page 52 Page 52 ...
Страница 93: ...93 HCD CP500K CP500MD MEMO ...