Sony CA-702, Руководство по обслуживанию

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4-7
CA-702
CA-702P
IC
S/H
AMP.
COURSE
CONPARATE
& ENCODE
DAC
TIMING
GEN.
CALIVBRATION
UNIT
COURSE CORRECTION
& LATCH
FINE
COMPARATE
& ENCODE
FINE LATCH
+
AV
DD
( + 5 V)
DGND
DGND DV
DD
(
+
3 V)
(LSB)
( + 3 V)
DGND
AGND
+
_
AMP.
( x 8)
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
TSTR
AT
VIN
CAL
TS
CE
OE
CLK
MINV
LINV
TMOD
SEL
RESET
TIN
TO
1 2 3 4 5 6 7 8 9
10 11 12
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
36 35 34 33 32 31 30 29 28 27 26 25
VRB VRB VRT VRT
NC NC NC
AGND AGND
AV
DD
AV
DD
(
+
5 V)
(
+
5 V)
NC
AGND
AGND
DV
DD
NC
NC
C-MOS 10-BIT 20 MSPS VIDEO A/D CONVERTER
—TOP VIEW—
CXD2310AR-T4 (SONY) CXD3122R (SONY)
37
38
39
40
41
42
43
44
45
46
47
48
V
DD ( + 3.0 to + 5.5 V)
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
V
DD (
+
3.0 to
+
5.5 V)
NC
NC
NC
NC
36 35 34 33 32 31 30 29 28 27 26 25
GND
1 2 3 4 5 6 7 8 9
10 11 12
GND
1
2
3
4
5
7
8
9
10
11
12
21
20
18
17
16
15
14
13
24
23
22
37
39
40
42
48
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
COMP
PSW0
PSW1
PSW2
PSW3
PSW4
PSW5
PSW6
PSW7
PSB0
PSB1
PSB2
STB
AEN
NTSC/PAL
CLK
TEST
DOT0
DOT1
DOT2
DOT3
DOT4
DOT5
DOT6
DOT7
DOT8
DOT9
36
35
34
33
32
31
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
I
I
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
—
I
I
I
I
I
DIN0
DIN1
DIN2
DIN3
DIN4
GND
DIN5
DIN6
DIN7
DIN8
DIN9
COMP
PSW7
PSW6
PSW5
PSW4
PSW3
PSW2
V
DD
PSW1
PSW0
PSB2
PSB1
PSB0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
O
O
O
O
—
O
O
O
O
O
O
I
—
I
I
—
I
—
—
—
—
—
I
OEN
DOT9
DOT8
DOT7
DOT6
GND
DOT5
DOT4
DOT3
DOT2
DOT1
DOT0
STB
NC
AEN
NTSC/PAL
NC
CLK
V
DD
NC
NC
NC
NC
TEST
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
(V
DD
= + 3.3 to + 5.5 V)
C-MOS DIGITAL LINE MEMORY
—TOP VIEW—
25
OEN
; CALIBRATION PULSE INPUT
; CHIP ENABLE
; CLOCK
; OUTPUT (D0 - D8) INVERSION
; OUTPUT (D9) INVERSION
; DIGITAL DATA OUTPUT ENABLE
; CALIBRATION CIRCUIT RESET
; OUTPUT DATA (D5 - D9) SELECT FOR CALIBRATION (4-CLOCK)
HIGH ; THROUGH OUTPUT, OW ; DATA FIXED AS WITH D0 - D4
; TEST SIGNAL INPUT
; TEST MODE
; TEST SIGNAL INPUT
; TEST SIGNAL INPUT
; REFERENCE BOTTOM VOLTAGE
; REFERENCE TOP VOLTAGE
; TEST SIGNAL OUTPUT
; DIGIRAL DATA OUTPUT
; TEST PIN
INPUT
CAL
CE
CLK
LINV
MINV
OE
RESET
SEL
TIN
TMOD
TS
TSTR
VRB
VRT
OUTPUT
AT
D0 - D9
TO
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TO
AT
VRT
VRT
VIN
VRB
VRB
CAL
SEL
RESET
CE
OE
CLK
TIN
TSTR
TS
12
11
10
9
8
5
4
3
2
1
13
38
29
30
39
34
35
41
17
15
24
23
22
14
37
42
INPUT
AEN
CLK
COM
DIN0 - DIN9
NTSC/PAL
OEN
PSB0 - PSB2
PSW0 - PSW7
STB
TEST
OUTPUT
DOT0 - DOT9
: AMOUNT OF DELAY SELECT
: CLOCK
: COMPATIBILITY SELECT
: DATA
: AMOUNT OF DELAY FOR NTSC/PAL/SECAM SELECT
: OUTPUT ENABLE
: NUMBER OF SMALL DELAY SETTING
: NUMBER OF DELAY SETTING
: STANDBY
: TEST
: DATA
BUFFER
1-LINE
MEMORY
(1138 x 10-BIT)
SMALL
DELAY
CONTROLLER
BUFFER DIN0 - DIN9
1 - 5,
7 - 11
DOT0 - DOT9
26 - 29,
31 - 36
ADDRESS
COUNTER
ADDRESS
MULTIPLEXER
TIMING
CONTROLLER
PSW0 - PSW7
13 - 18, 20, 21
NTSC/PAL
40
AEN
39
TEST
48
COMP
12
STB
37
CLK
42
TEST
OEN
25
PSB0 - PSB2
22 - 24
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