Sony BDKP-N1001, Руководство по обслуживанию

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3-3
BDX-N1000
IC
IC
78P7200-IH (TDK SEMI)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
—
I
—
I
—
—
—
O
—
O
I
I
I
I
I
—
I
I
I
—
—
O
O
O
—
O
I
LIN +
NC
LIN _
NC
RFO
GND
V
CC
GND
LOUT +
NC
LOUT _
LBO
OPT1
TPOS
TNEG
TCLK
V
CC
OPT2
LF1
LF2
NC
GND
RCLK
RNEG
RPOS
V
CC
LOWSIG
CPD
PIN
NO.
PIN
NO.
I/O I/O SIGNAL SIGNAL
INPUTS
CPD
LBO
LF1, LF2
LIN + , LIN _
OPT1
,
OPT2
RFO
TCLK
TNEG
TPOS
OUTPUTS
LOUT +
LOUT _
LOWSIG
RCLK
RNEG
RPOS
OTHER
NC
: EXTERNAL CAPACITOR
: TRANSMITTER LINE BUILDOUT
CONTROL
: FILTER NETWORK
: DIFFERENTIAL SIGNAL
: TRANSMIT OPTION 1, 2
: EXTERNAL REGISTER
: TRANSMITTER CLOCK
: TRANSMITTER NEGATIVE DATA
: TRANSMITTER POSITIVE DATA
: POSITIVE DATA PULSE
: NEGATIVE DATA PULSE
: LOW SIGNAL
: RECOVERED CLOCK
: RECEIVER NEGATIVE PULSE
: RECEIVER POSITIVE PULSE
: NO CONNECT
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12 13 14 15 16 17 18
4 3 2 1 28 27 26
DS3/E3/STS-1 LINE INTERFACE WITH RECEIVE EQUALIZER
—TOP VIEW—
CAS9053 (COMATLAS)
AAL1 VIDEO ERROR PROCESSOR
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
I/O
—
—
—
I/O
I/O
I/O
I/O
—
I
I
I
I
I
I
—
—
DUP3
V
CC
GND
GND
DUP4
DUP5
DUP6
DUP7
V
CC
ADR2
ADR1
ADR0
TRST
TMS
TDI
RESERVED
GND
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
—
I
O
I
I
—
I
I
I
I
I
—
I
I
I
I
—
GND
MODE
ENR
TCK
RESET
GND
NOR4
NOR3
NOR2
NOR1
NOR0
GND
DIN7
DIN6
DIN5
DIN4
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
I
—
—
—
—
I
I
I
I
I
I
O
O
O
O
O
—
CLK
V
CC
V
CC
GND
GND
DIN3
DIN2
DIN1
DIN0
SCOR
/F
ENNOR
TDO
DOUT0
DOUT1
DOUT2
DOUT3
V
CC
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
—
—
O
O
O
O
O
O
O
O
I
—
I
I
I/O
I/O
I/O
V
CC
GND
DOUT4
DOUT5
DOUT6
DOUT7
MATSTART
UNCORR
FUS
FTOT
CSEL
V CC
RD
WR
DUP0
DUP1
DUP2
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
SN AND SNP
COMPUTATION,
DEINTERLEAVING
SYNCHRO
AND
SUPERVISION
DIN7 - DIN0
CLK
RESET
NOR4 - NOR0
DUP0 - DUP7
ADR2 - ADR0
CSEL
WR
RD
SCOR
ENNOR
30 - 33,
40 - 43
DIN7 - DIN0
F
30 - 33,
40 - 43
66 - 68,
1, 5 - 8
24 - 28
44
45
ENR
20
44
10 - 12
62
65
64
DUP0 - DUP7
ADR2 - ADR0
CSEL
WR
RD
66 - 68,
1, 5 - 8
10 - 12
62
65
64
35
22
CLK
RESET
35
22
8
8
DOUT0 -DOUT7
FTOT
FUS
UNCORR
MATSTART
47 - 50,
54 - 57
47 - 50,
54 - 57
61
60
59
58
DOUT0 -DOUT7
FTOT
FUS
MATSTART
61
60
58
DEINTERLEAVING
MATRICES
INTERLEAVING
MATRICES
SAR-PDU
HEADER
ADDER
REED-SOLOMON
DECODER
(128,124)
WITH ERASURES
MONITORING
FIFO
INTERFACE
RECEPTION (MODE = 0)
u
P REGISTERS
AUTOTEST
DELAY LINE
8 8
8
3
8
8
8
8
8
8
8
8
5
REED-SOLOMON
ENCODER
(128,124)
TRANSMISSION (MODE = 1)
AUTOTEST
u
P REGISTERS
8
8
3
8
8
8
8
8
8
CLC014AJE-TR (NS)
8
9
12
6
7
DI
DI
MUTE
AEC +
AEC
_
13
14
3
5
DO
DO
OEM
CD
INPUTS
AEC +
AEC _
DI,
DI
MUTE
OUTPUTS
CD
DO,
DO
OEM
: ADAPTIVE EQUALIZER CAPACITOR (POSITIVE)
: ADAPTIVE EQUALIZER CAPACITOR (NEGATIVE)
: DATA
: MUTING
: CARRIER DETECT
: DATA
: OUTPUT EYE MONITOR
DI
8
V
CC
V
CC
OEM
V
CC
CD
AEC +
AEC _
1
2
3
4
5
6
7
14
13
12
11
10
9
8
DO
DO
MUTE
GND
GND
DI
DI
ADAPTIVE CABLE EQUALIZER FOR HIGH-SPEED DATA RECOVERY
—TOP VIEW—
OEM BUFFER
QUANTIZED
FB COMPARATOR
EQUALIZER
DI
9
DO
13
DO
14
OEM
3
ADAPTIVE
SERVO CONTROL
MUTE
12
6
AEC +
7
AEC _
CD
5
EQ.
LIN +
LIN _
LOWSIG
1
3
LF1
LF2
CPD
RFO
19
20
28
5
27
RCLK
23
RPOS
RNEG
25
24
TCLK
TPOS
TNEG
16
14
15
OPT1
OPT2
LBO
13
18
12
SIGNAL
ACQUISITION
PULSE
GENERATOR
PULSE
SHAPER
OUTPUT
DRIVER,
LINE
BUILDOUT
DATA
DETECTION
LOUT +
LOUT _
9
11
CLOCK
RECOVERY
LOW-LEVEL SIGNAL
DETECTION