Sony BDKP-N1001, Руководство по обслуживанию

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3-10
BDX-N1000
IC
IDT77155L155PX (IDT)
103
105
110
115
120
125
128
ATM USER-NETWORK INTERFACE
—TOP VIEW—
64
60
55
50
45
40
39
102 100 95 90 85 80 75 70 65
1 5
10 15 20 25 30 35 38
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
—
I
I/O
—
—
—
—
—
I
I
—
—
O
O
O
O
—
—
—
—
—
O
O
—
I
I
I
I
—
—
—
—
GND
TBYP
ATP2
TAVD1
TAVS1
TAVD2
TAVS2
TAVD3
TRCLK _
TRCLK +
TAVS3
TXV
CC
TXC +
TXC
_
TXD +
TXD _
TXGND
V
CC
GND
V
CC
GND
RXDO +
RXDO _
RAVD3
RXD _
RXD +
ALOS _
ALOS +
RAVS3
RAVD1
RAVS1
RAVD4
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I
I
—
—
—
—
—
I/O
I
I/O
I/O
I/O
—
—
—
—
—
I
O
I
O
O
—
—
O
O
O
O
—
—
O
—
RRCLK _
RRCLK +
RAVS4
RAVD2
RAVS2
GND
GND
ATP1
RBYP
LF +
LF _
LFO
GND
GND
GND
GND
GND
XOFF
TCP
TGFC
TFPO
TCLK
V
CC
GND
RCLK
RFP
RGFC
RCP
V
CC
GND
RALM
GND
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
—
I
I
I
O
O
O
—
—
O
O
O
O
O
O
—
—
O
O
I
I
O
I
I
I
I
I
I
I
I
I
I
GND
TSEN
RFCLK
RRDENB
RCA
RDAT0
RDAT1
GND
V
CC
RDAT2
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
GND
V
CC
RXPRTY
RSOC
TFCLK
TWRENB
TCA
TDAT0
TDAT1
TDAT2
TDAT3
TDAT4
TDAT5
TDAT6
TDAT7
TXPRTY
TSOC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
I
I
I
I
I
—
—
I
I
—
—
O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
—
RATE1
RATE0
VCLK
CSB
RSTB
GND
GND
WRB
RDB
GND
V
CC
INTB
D0
D1
D2
D3
GND
V
CC
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7/TRS
ALE
GND
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
INPUTS
A0 - A7
ALE
ALOS + , ALOS _
CSB
RATE0, RATE1
RBYP
RDB
RFCLK
RRCLK + , RRCLK _
RRDENB
RSTB
RXD + , RXD _
TBYP
TDAT0 - TDAT7
TFCLK
TGFC
TRCLK + , TRCLK _
TXPRTY
TSEN
TSOC
TWRENB
VCLK
WRB
XOFF
OUTPUTS
INTB
RALM
RCA
RCLK
RCP
RDAT0 - RDAT7
RFP
RGFC
RSOC
RXDO + , RXDO _
RXPRTY
TCA
TCLK
TCP
TFPO
TXC + , TXC _
TXD + , TXD _
INPUTS/OUTPUTS
ATP1, ATP2
D0 - D7
LF + , LF _
LFO
: ADDRESS BUS
: ADDRESS LATCH ENABLE
: ANALOG LOSS
: CHIP SELECT
: FRAME FORMAT AND LINE RATE SELECT
: RECEIVE BYPASS
: READ ENABLE
: RECEIVE READ CLOCK
: RECEIVE DIFFERENTIAL REFERENCE CLOCK
: RECEIVE READ ENABLE
: RESET
: RECEIVE DIFFERENTIAL DATA
: TRANSMIT BYPASS
: TRANSMIT CELL DATA
: TRANSMIT WRITE CLOCK
: TRANSMIT GENERIC FLOW CONTROL
: TRANSMIT DIFFERENTIAL REFERENCE CLOCK
: TRANSMIT PARITY
: TRISTATE ENABLE
: TRANSMIT START OF CELL
: TRANSMIT WRITE ENABLE
: VECTOR CLOCK
: WRITE STROBE
: TRANSMIT OFF
: INTERRUPT
: RECEIVE ALARM
: RECEIVE CELL AVAILABLE
: RECEIVE CLOCK
: RECEIVE GENERIC FLOW CONTROL CELL PULSE
: RECEIVE CELL DATA
: RECEIVE FRAME PULSE
: RECEIVE GENERIC FLOW CONTROL
: RECEIVE START OF CELL
: RECEIVE DIFFERENTIAL DATA
: RECEIVE PARITY
: TRANSMIT CELL AVAILABLE
: TRANSMIT BYTE CLOCK
: TRANSMIT GENERIC FLOW CONTROL CELL PULSE
: FRAMING POSITION
: TRANSMIT CLOCK
: TRANSMIT DIFFERENTIAL DATA
: ANALOG TEST
: DATA BUS
: LOOP FILTER
: LOOP FILTER
DATA
RECOVERY
10
9
13
14
15
16
98
97
3
2
RATE0
RATE1
ATP2
TBYP
TRCLK +
TRCLK _
TXC +
TXC _
TXD +
TXD _
26
25
22
23
RXD
+
RXD _
RXDO
+
RXDO _
34
33
RRCLK +
RRCLK _
28
27
41
40
42
43
44
57
63
58
RBYP
ATP1
LF +
LF _
LFO
RCLK
RALM
RFP
ALOS +
ALOS _
TSOC
TXPRTY
TDAT0 - TDAT7
TCA
TWRENB
TFCLK
TCLK
TFPO
TCP
TGFC
XOFF
RSOC
RXPRTY
RDAT0 - RDAT7
RCA
RRDENB
RFCLK
TSEN
INTB
RSTB
RDB
WRB
CSB
ALE
A0 - A7
D0 - D7
RCP
RGFC
83
82
70, 71
74 - 79
69
68
67
66
108
101
105
104
100
127
119 - 126
109 - 112, 115 - 118
60
59
96
95
87 - 94
86
85
84
54
53
51
52
50
8
DRIVER
CLK GEN.
CLK REC.
TX ATM
CELL
PROCESSOR
TX
ATM
CELL
FIFO
RX
ATM
CELL
FIFO
PARALLEL
TO
SERIAL
TX FRAMER
AND
OVERHEAD
PROCESSOR
RX ATM
CELL
PROCESSOR
SERIAL
TO
PARALLEL
RX FRAMER
AND
OVERHEAD
PROCESSOR
MICROPROCESSOR
I/F
8
8
8
LC35256DM-70-TLM (SANYO)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
IN
A12
IN
A7
IN
A6
IN
A5
IN
A4
IN
A3
IN
A2
IN
A1
IN
A0
IN
D0
I/O
D1
I/O
D2
I/O
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WE
IN
A13
IN
A8
IN
A9
IN
A11
IN
OE
IN
A10
IN
CS
IN
D7
I/O
D6
I/O
D5
I/O
D4
I/O
D3
I/O
V
DD
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
WE
27
CS
20
OE
22
A0 - A14
D0 - D7
CS
OE
WE
0
1
x
HI-Z
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
: ADDRESS INPUTS
: DATA INPUTS/OUTPUTS
: CHIP SELECT INPUT
: OUTPUT ENABLE INPUT
: WRITE ENABLE INPUT
CS
1
0
0
0
OE
x
1
0
x
WE
x
1
1
0
OUTPUTS
HI-Z
HI-Z
D
OUT
D
IN
FUNCTION
NO SELECTION
OUTPUT DISABLE
READ
WRITE
C-MOS 256 K (32,768WORD x 8)-BIT SRAM
—TOP VIEW—