Sony AIT-SDX460, Руководство по техническим характеристикам продукции

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5. ATA/ATAPI Interface
SONY AIT-1 Turbo drive SDX-460V series Ver.1.0 5-2
5.2.1. Device Registers
The Command Block registers are used for sending commands to the device or posting status from the device.
These registers include the Cylinder High, Cylinder Low, Device/Head, Sector Count, Sector Number, Command,
Status, Features, Error, and Data registers. The Control Block registers are used for device control and to post an
alternate status. These registers include the Device Control and Alternate Status registers.
Alternate Status register
This register contains the same information as the Status register in the command block.
Command register
7 6 5 4 3 2 1 0
Command Code
This register contains the command code being sent to the device. Command execution begins immediately after
this register is written.
Cylinder High register
The content of this register is command dependent and becomes a command parameter when the Command
register is written.
Cylinder Low register
The content of this register is command dependent and becomes a command parameter when the Command
register is written.
Data port
The data port is 16-bits in width. DMA out data transfers are processed by a series of reads to this port, each read
transferring the data that follows the previous read. DMA in data transfers are processed by a series of writes to
this port, each write transferring the data that follows the previous write.
Data register
The data register is 16-bits wide. PIO out data transfers are processed by a series of reads to this register, each
read transferring the data that follows the previous read. PIO in data transfers are processed by a series of writes
to this register, each write transferring the data that follows the previous write.
Device Control register
This register allows a host to software reset attached devices and to enable or disable the assertion of the INTRQ
signal by a selected device. When the Device Control register is written, both devices respond to the write
regardless of which device is selected. When the SRST bit is set to one, both devices shall perform the software
reset protocol. The device shall respond to the SRST bit when in the SLEEP mode. When the nIEN bit is set or
cleared, both devices shall disable or enable assertion of the INTRQ signal.
7 6 5 4 3 2 1 0
r r r r r SRST nIEN 0
- Bits 7 through 3 are reserved.
- SRST is the host software reset bit.
- nIEN is the enable bit for the device interrupt to the host. When the nIEN bit is cleared to zero, and the
device is selected, INTRQ shall be enabled through a tri-state buffer and shall be asserted or negated by
the device as appropriate. When the nIEN bit is set to one, or the device is not selected, the INTRQ signal
shall be in a high impedance state.
- Bit 0 shall be cleared to zero.