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MANUAL
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2.3.7.1.2 Timing
Timing shall be according to the following diagram. The signals in the diagram shall be interpreted according to the
following relation.
GM-41 Signal
Direction
PCMCLK
Output from module
PCMSYNC Output
from
module
PCMULD
Input to module
PCMDLD Output
from
module
Table 24: PCM Timing Diagram
Figure 10: PCM timing diagram
Name
Description
Min.
Nom.
Max.
Units
PCMCLK clock
frequency
200
kHz
PCMSYN
PCM sync frequency
8
kHz
t
PSS
PCMSYN (setup) to PCMCLK (fall)
10
ns
t
PSH
PCMSYN pulse length
20
ns
t
DSL
PCMULD (setup) to PCMCLK (fall)
10
ns
t
DSH
PCMULD (hold) from PCMCLK (fall)
10
ns
t
PDLP
PCMDLD valid from PCMCLK (rise)
25
ns
Table 25: PCM timing parameters
A PCM data frame consists of 16 data bits. There are 19 clock periods sent out on the PCMCLK output. The initial
three clock periods are for stabilization. They are followed by a sync pulse on PCMSYNC together with 16 clock
periods. The PCMCLK line is then inactive until three clock periods before the next frame sync.
