Note:
All these register fields are 15 bits wide. Therefore, the fraction will need to truncate to up to this precision. This section fully
determines the VCO frequency, the P-divider and the feedback divider for this plan given the choice of using O-dividers {HSDIV} for
M-2 output clocks and N-dividers {ID} for two output clocks.
The next step will be to determine the closed loop response that is required from the PLL. The table below lists the different loop BW
settings possible and the register field value that will enable that loop BW setting:
Table 6.4. Loop BW Options
PLL_MODE
Loop Bandwidth (kHz)
PLL. Ref. Freq. Min (MHz)
PLL. Ref. Freq. Max. (MHz)
0
ILLEGAL IF PLL MODE IS ENABLED
1
350
10
15
2
250
10
15
3
175
10
15
4
500
15
30
5
350
15
30
6
250
15
30
7
175
15
30
8
500
30
50
9
350
30
50
10
250
30
50
11
175
30
50
This algorithm will result in a final solution for a VCO frequency, vcoFreq, that can then be used to calculate the O-divider , N-divider,
and R-divider values needed to derive each output frequency, Fx.
Si5357 Reference Manual • Programming the Volatile Memory
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021
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