SiTime SiT6502EB, Руководство пользователя

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SiT6502EB HW UM Preliminary Rev 1.0 Page 11 of 33 www.sitime.com
SiT6502EB Evaluation Board (EVB) HW User Manual
Table 7. Output Port Not Populated Resistors
Output Port # 0 1 2 3 4 5 6 7 0B 0T
Not Populated
Resistors R113
R117 R114
R118 R115
R119 R116
R120 R129
R133 R130
R134 R131
R135 R132
R136 R143
R145 R144
R146
11.1.2 LVPECL
For LVPECL output configuration ceramic capacitors 0.1 uF are placed instead of correspondent series
resistors RSExx (Refer to
Table 6 ). Termination resistor values depending on the output driver VDD level
are shown in Table 8.
Table 8. Output Port Termination Resistors for LVPECL
Output Port # 0 1 2 3 4 5 6 7 0B 0T
Resistors
R113
R117 R114
R118 R115
R119 R116
R120 R129
R133 R130
R134 R131
R135 R132
R136 R143
R145 R144
R146
VDD, 3.3V 150

150

150

150

150

150

150

150

150

150

VDD, 2.5V 120

120

120

120

120

120

120

120

120

120

Also, ensure that jumpers JSCLxx as per Table 9 are populated to allow path to GND.
Table 9. Output Port Jumpers to GND
Output Port # 0 1 2 3 4 5 6 7 0B 0T
Jumpers to GND JSCL13 JSCL14 JSCL15 JSCL16 JSCL17 JSAL18 JSCL19 JSCL20 JSCL21 JSCL22
11.1.3 HCSL
For HCSL output configuration series resistors RSExx (Refer to Table 6 ). 33

should be used for each
output port. Please note each lane per pair should be terminated by 50

to GND on the receiver side.
12
Quick Start
- Install Time Master for Clocks GUI on your Windows PC
- Confirm jumpers are installed as shown in Table 3
- Connect a USB cable from SiT6502EB, J3 to your PC
- Launch the Time Master for Clocks GUI
- Refer to the accompanying Time Master for Clocks SW User Manual to configure your frequency
plan on the SiT6502EB
- Default Output Driver Configuration is LVDS and Output Driver Supplies are configured to 3.3V