SiT6502EB HW UM Preliminary Rev 1.0
Page 10 of 33
SiT6502EB Evaluation Board (EVB) HW User Manual
Figure 7. Output Clock Termination Circuit
11.1
Output Differential Termination
LVDS (default configuration), LVPECL, HCSL, and CML differential signaling types can be supported by
changing the output termination circuits.
11.1.1
LVDS, CML
The board is shipped to support LVDS, CML in its default differential. The signals are ac coupled with
ceramic 0.1 uF capacitors instead of the corresponding series resistors RSExx (Refer to
) which
are not populated.
Table 6. Output Port RSExx Resistors
Output Port #
0
1
2
3
4
5
6
7
0B
0T
0.1 uF capacitors
RSE1
RSE5
RSE2
RSE6
RSE4
RSE7
RSE3
RSE8
RSE10
RSE14
RSE9
RSE13
RSE11
RSE15
RSE12
RSE16
RSE17
RSE19
RSE18
RSE20
Output termination resistors as shown in
are not populated.
CSE6
10pF
VCM_1
JSCL14
JSCL2
1
2
DNP
J44
CONNECTOR COAX-P_3PIN
1
2
3
DNP
CLK1_OUT_P
GND
VC
M
_1
CLK1_DUT_N
GND
R118
49.9
DNP
CLK1_DUT_P
DNP
GND
R111
0
R123
0
CLK1_OUT_N
RSE2
453E
C71
10 uF
DNP
CLK1_DUT_P
CSE2
10pF
DNP
C70
1 uF
GND
CLK1_OUT_P
CLK1_DUT_N
J49
CONNECTOR COAX-P_3PIN
1
2
3
CLK1_OUT_N
RSE6
453E
R114
49.9