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8317
8317
N/B Maintenance
N/B Maintenance
5.2 ATI RS480M North Bridge(7)
Power Pins
Pin Name
Voltage
Pin
Count
Ball Reference
Comments
AVDD
2.5V or
3.3V
2
B27, C27
Dedicated power for the DAC. Effort
should be made at the board level to
provide as clean a power as possible to this
pin to avoid noise injection, which can
affect display quality. Adequate
decoupling should be provided between
this pin and AVSS.
AVDDQ
1.8V
1
E24
DAC Bandgap Reference Voltage
AVDDDI
1.8V
1
C24
Dedicated digital power for the DAC
VDD_CORE
1.2V
47
A22, B21, B22, C21,
C22, D21, D22, E21,
E22, F21,
F22, G21, G22, H21,
H22, M13, M15,
M17, M19, N12,
N14, N16, N18, P13,
P15,
P17, P19, R12, R14,
R16, R18, T13, T15,
T17, T19, U12, U14,
U16, U18, V13, V15,
V17, V19, W12,
W14, W16, W18
Core power
VDD_18
1.8V
3
AC15, AC17, H15
I/O Transform Power for memory, CPU,
and GPIO sections.
VDDA_12
1.2 V
14
AA7, AA8, B1, F9,
G7, G8, G9, H9, J7,
J8, N7, N8, U7, U8
PCI Express interface main I/O power
VDDA_18
1.8V
13 AC7,
AC8,
AE6,
AF5, AF6, AG4,
AK2, L7, L8, R7,
R8, W7, W8
PCI Express interface power for output Tx
stage
VDD_MEM 1.8 / 2.5V
18
AC10, AC12, AC14,
AC18,
AC20, AC22, AD10,
AD12,
AD14, AD15, AD18,
AD20,
AD22, AE30, AK11,
AK23,
AK28, AK4
Isolated IO power for memory interface
Power Pins (Continued)
Pin Name
Voltage
Pin
Count
Ball Reference
Comments
VDD_MEM
CK
1.8 / 2.5V
1
AH15
IO Power for memory clocks
VDD_HT
1.2V
31
A23, A29, AA23,
AA27, AB23, AB24,
AB27, AC30, B23,
C23, D23, E23, F23,
G23, G27, H23, H27,
J23, J27, K23, K24,
K27, N27,
P24, P27, U23, U27,
V23,V24,V27,W23
IO power for HyperTransport interface
VDDR3
3.3V
2
H12, H13
IO power for the following I/O pads:
OSC, POWERGOOD, SYSRESET#
LPVDD
1.8V
1
E18
Power for LVDS PLL macro.
LVDDR18D
1.8V
1
E19
1.8V LVDS Digital Power
LVDDR18A
1.8V
2
G20, H20
1.8V LVDS Analog Power
PLLVDD
1.8V
1
A14
Power for PLL
HTPVDD
1.8V
1
M23
Power for HyperTransport interface PLL
MPVDD
1.8V
1
AJ15
Power for memory interface PLL
Total Power Pin Count
140
1 x 2 Lane A-Link Express Interface for IXP
Pin Name Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
SB_TX[1:
0]P,
SB_TX[1:
0]N
O
VDDA_1
8
VSSA
50
Ω
between
complements
Transmit Data Differential Pairs. Connect
to the corresponding
Receive Data Differential pairs on the
IXP.
SB_RX[1:
0]P,
SB_RX[1:
0]N
I
VDDA_1
8
VSSA
50
Ω
between
complements
Receive Data Differential Pairs. Connect
to the corresponding
Transmit Data Differential pairs on the
IXP.
SB_CLKP
,
SB_CLK
N
I/O
VDDA_1
8
VSSA
50
Ω
between
complements
Clock Differential Pair. Connect to an
external clock generator on the
motherboard.