86
8317
8317
N/B Maintenance
N/B Maintenance
5.2 ATI RS480M North Bridge(1)
CPU Interface
Pin Name Type
Power
Domain
Ground
Domain
Functional Description
HT_RXC
AD[15:0]
P,
HT_RXC
AD[15:0]
N
I
VDDHT
VSS
Receiver Command, Address, and Data Differential Pairs
HT_RXC
LK[1:0]P,
HT_RXC
LK[1:0]N
I
VDDHT
VSS
Receiver Clock Signal Differential Pair. Forwarded clock
signal. Each byte of RXCAD uses a different clock signal.
Data is transferred on each clock edge.
HT_RXC
TLP,
HT_RXC
TLN
I
VDDHT
VSS
Receiver Control Differential Pair. For distinguishing
control packets from data packets.
HT_TXC
AD[15:0]
P,
HT_TXC
AD[15:0]
N
O
VDDHT
VSS
Transmitter Command, Address, and Data Differential
Pairs
HT_TXC
LK[1:0]P,
HT_TXC
LK[1:0]N
O
VDDHT
VSS
Transmitter Clock Signal Differential Pair. Each byte of
TXCAD uses a different clock signal. Data is transferred on
each clock edge.
HT_TXC
TLP,
HT_TXC
TLN
O
VDDHT
VSS
Transmitter Control Differential Pair. Forwarded clock
signal. For distinguishing control packets from data
packets.
HT_RXC
ALN
Other
VDDHT
VSS
Receiver Calibration Resistor to VDD_HT power rail.
HT_RXC
ALP
Other
VDDHT
VSS
Receiver Calibration Resistor to Ground
HT_TXC
ALP
Other
VDDHT VSS Transmitter Calibration Resistor to HTTX_CALN
HT_TXC
ALN
Other
VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP
HTREFC
LK
I
HTPVDD HTPVSS HyperTransport 66 MHz reference clock from external
clock source
HTTSTCL
K
I
HTPVDD HTPVSS HyperTransport Bus Test Clock. Drives test clock in test
mode. Connect to ground in functional mode.
GDDR Side-Port Memory Interface
Pin Name Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
MEM_A[
14:0]
O
VDD_M
EM
VSS
None
Memory Address Bus. Provides the
multiplexed row and column addresses to
the memories.
MEM_RA
S#
O
VDD_M
EM
VSS
None
Row Address Strobe
MEM_CA
S#
O
VDD_M
EM
VSS
None
Column Address Strobe
MEM_W
E#
O
VDD_M
EM
VSS
None
Write Enable Strobe
MEM_CK
E
O
VDD_M
EM
VSS None
Clock
Enable
MEM_CK
P
O
VDD_M
EM
VSS
None
Memory Differential Positive Clock
MEM_CK
N
O
VDD_M
EM
VSS
None
Memory Differential Negative Clock
MEM_CS
#
O VDD_M
EM
VSS None
Chip
Select
MEM_DQ
[63:0]
I/O
VDD_M
EM
VSS
None
Memory Data Bus. Supports SSTL2 and
SSTL3.
MEM_D
M[7:0]
I/O
VDD_M
EM
VSS
None
Data masks for each byte during memory
write cycles
MEM_DQ
S[7:0]P
I/O
VDD_M
EM
VSS
None
GDDR Data Strobes. These are
bi-directional data strobes for latching
read/write data.
MEM_DQ
S[7:0]N
I/O
VDD_M
EM
VSS
None
Do not connect.
MEM_V
MODE
I
–
VSS
None
Selects Memory I/O type. This pin must
be tied to the appropriate level depending
on the memories connected to the
interface.
For VDD_MEM=2.5V, connect
MEM_VMODE 0V.
For VDD_MEM=1.8V, connect
MEM_VMODE to 1.8V.
NOTES:
(1) All DRAM connected must
be of the SAME interface type; (2) In
Sleep mode, when the memory power is
on and when MEM_VMODE selects
VDD_MEM=1.8V, MEM_VMODE pad
MUST ALSO have 1.8V applied to it.
