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8317
8317
N/B Maintenance
N/B Maintenance
An external clock signal divided by TMR_1 can be used as the FRT capture input signal
An internal synchronization signal can be generated using the FRT and TMR_Y
A signal generated/modified using an input signal and timer connection can be selected and output
Watchdog Timer (WDT)
Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks
Switchable between watchdog timer mode and interval timer mode
Watchdog Timer Mode
Internal Timer Mode
Serial Communication Interface (SCI and IRDA)
Choice of asynchronous or clocked synchronous serial communication mode
Full-duplex communication capability
The on-chip baud rate generator allows any bit rate to be selected
Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
Four interrupt sources