Sinty Zhang 8317, Руководство по обслуживанию

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88
8317
8317
N/B Maintenance
N/B Maintenance
5.2 ATI RS480M North Bridge(3)
LVDS Interface
Pin Name Type Power
Domain
Ground
Domain Integrated
Termination
Functional Description
TXOUT_
U0N O LVDDR1
8A
LVSSR None LVDS upper data channel 0 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode
TXOUT_
U0P O LVDDR1
8A
LVSSR None LVDS upper data channel 0 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXOUT_
U1N O LVDDR1
8A
LVSSR None LVDS upper data channel 1 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXOUT_
U1P O LVDDR1
8A
LVSSR None LVDS upper data channel 1 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXOUT_
U2N O LVDDR1
8A
LVSSR None LVDS upper data channel 2 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXOUT_
U2P O LVDDR1
8A
LVSSR None LVDS upper data channel 2 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXOUT_
U3N O LVDDR1
8A
LVSSR None LVDS upper data channel 3 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXOUT_
U3P O LVDDR1
8A
LVSSR None LVDS upper data channel 3 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. Only used
in dual-channel LVDS mode.
TXCLK_
UN O LVDDR1
8A
LVSSR None LVDS upper clock channel (-)
Transmitting at pixel clock rate, up to
85MHz pixel clock. Only used in
dual-channel LVDS mode.
TXCLK_
UP O LVDDR1
8A
LVSSR None LVDS upper clock channel (+)
Transmitting at pixel clock rate, up to
85MHz pixel clock. Only used in
dual-channel LVDS mode.
LVDS Interface (Continued)
Pin Name Type Power
Domain
Ground
Domain Integrated
Termination
Functional Description
TXOUT_
L0N O LVDDR1
8A
LVSSR None LVDS lower data channel 0 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L0P O LVDDR1
8A
LVSSR None LVDS lower data channel 0 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L1N O LVDDR1
8A
LVSSR None LVDS lower data channel 1 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L1P O LVDDR1
8A
LVSSR None LVDS lower data channel 1 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L2N O LVDDR1
8A
LVSSR None LVDS lower data channel 2 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L2P O LVDDR1
8A
LVSSR None LVDS lower data channel 2 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L3N O LVDDR1
8A
LVSSR None LVDS lower data channel 3 (-)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.
TXOUT_
L3P O LVDDR1
8A
LVSSR None LVDS lower data channel 3 (+)
Transmitting at a bit rate of 7x pixel
clock, up to 85MHz pixel clock. This
channel is used as the transmitting channel
in single channel LVDS mode.