2. EFR RF Architecture Overview
The EFR32 chip family has separate sub-GHz and 2.4 GHz RF front ends. The sub-GHz part is not detailed here. The 2.4 GHz RF front
end architecture of the EFR32 chip is shown in the figure below.
The 2.4 GHz front end has a unified, single-ended TX and RX pin (2G4RF_IOP), so the TX and RX paths are tied together internally.
The 2G4RF_ION TX pin has to be grounded at the pin. It should consist of a good RF ground with multiple parallel GND vias.
Radio Transciever
2G4RF_IOP
2G4RF_ION
RF Frontend
PA
I
Q
LNA
BALUN
RFSENSE
Frequency
Synthesizer
DEMOD
AGC
IFADC
CR
C
BUF
C
MOD
FR
C
RA
C
PGA
Figure 2.1. 2.4 GHz Front End Configuration
The on-chip part of the front end comprises a variable (from 0 dBm to 20 dBm) power class AB differential PA, a variable PA tuning
cap, a differential LNA, an LNA/low-power PA match and protection circuit, and an integrated balun. The high-power PA is biased
through the PAV
DD
pin. Externally, a single-ended matching network and harmonic filtering are required.
AN930: EFR32 2.4 GHz Matching Guide
EFR RF Architecture Overview
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