Figure 3.7. 2-Element Lumped Element Match with Discrete Models of PCB Layout Parasitics
These PCB parasitics detune the matching network in the same way as the SMD parasitics described previously. Here, the further de-
crease of the applied series inductor (L0) to 1.8 nH and parallel capacitor (C0) to 1.1 pF compensates for the PCB parasitic effects.
Unfortunately, the harmonic suppression of the ladder two-element match is insufficient at the 20 dBm power level, so it is only used up
to 10 dBm. At power levels above 10 dBm, the ladder four-element match is required to comply with the harmonic restrictions of the
ETSI and FCC standards. However, below 10 dBm power levels, the ladder two-element match is advantageous because it has lower
cost and lower insertion loss compared to the ladder four-element match. Furthermore, if a dedicated match is designed for the low-
power regime, then it is useful to tune it to the optimum load-pull impedance of the 10 dBm power level, which is ~20 + j10 Ω as docu-
mented in
Appendix 1. PA Optimum Impedance Determination
and . The figure below shows the modified match (with L0 = 1.7 nH, C0
= 1.2 pF) to this new impedance.
Figure 3.8. 2-Element Match with SMD and PCB Layout Parasitics Tuned for the 10 dBm Power Level Optimum (20 + j10 Ω)
AN930: EFR32 2.4 GHz Matching Guide
2.4 GHz RF Matching Design Steps
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