Figure 3.10.a shows the EM simulated impedance of the ladder two-element match at the EFR32 TX pin (Port 2) together with the tar-
geted 10 dBm power impedance (~20 + j10 Ω). They are quite close. Here an L0 series inductance of 1.9 nH and a C0 parallel capaci-
tance of 1.5 pF is used as shown in the following table.
Table 3.1. Final SMD Values for the Ladder Two-Element Match
Two-element Matching Network
Schematic
Reference Designator
Component Value
Tolerance
Part Number
Manufacturer
LH0
1.9 nH
±0.05 nH
LQP15MN1N9W02
Murata
CH0
1.5 pF
±0.1 pF
GRM1555C1H1R5BA01D
Murata
Figure 3.10.b shows the simulated transfer characteristic from the TX pin to the 50 Ω output port. As expected, the second harmonic
suppression is sufficient only up to ~10 dBm fundamental power.
Figure 3.10. EM Simulation Results of the Ladder Two-Element SMD Match
AN930: EFR32 2.4 GHz Matching Guide
2.4 GHz RF Matching Design Steps
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