3.4.3 EM Simulations
As mentioned previously, the best accuracy can be achieved by EM simulations. However, this step can be skipped if the proper CAD
tool is not available. The EM simulated results shown here were created by an Axiem 3D planar simulator of AWR Corporation.
The figure below shows a simulated layout. This layout is used for both the ladder two-element and four-element matches. Here, the
2G4RF_IOP pin of the EFR32 chip is connected to Port 2. The L0 inductor is connected between Ports 3 and 4, the C0 capacitor be-
tween Ports 5 and 6, the L1 inductor between Ports 7 and 8, and the C1 capacitor between Ports 9 and 10. For the ladder two-element
match, a 0 Ω is connected to the place of L1 and the C1 and is not fitted.
Figure 3.9. EM Simulated Layout for the Discrete Lumped Element Matches
AN930: EFR32 2.4 GHz Matching Guide
2.4 GHz RF Matching Design Steps
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