S5-90U/S5-95U
Onboard Counter Inputs
11.5
Cascading Counters (with the S5-95U only)
Instead of using counter A and counter B individually and independently of each other, you can
combine them (cascading).
Use cascading of counters if you want to count amounts larger than 65,535 (up to 4,294,967,295).
The registers of both counters work together like a larger counter with more digits. The maximum
counting frequency for the counter cascade is 5 kHz if no programmers, operator panels or SINEC
L1/L2 are connected.
If you cascade counters, counter input B is automatically disabled; therefore, you must connect the
incoming pulses to counter input A. Section 3.3.5 describes how to connect a pulse generator to
counter input A.
•
Parameterizing the Counter Cascade in DB1
You specify in DB1
- Whether the counter cascade is to count the positive pulse edges or
- The negative pulse edges, and
- The value (comparison value) up to which the counter cascade is to count.
Example:
Setting parameters for counter cascade
Table 11-8. Setting Parameters for Counter Cascade
Set Parameters for Cascading Counter
Explanation
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
12: KS =' ; OBC: CCN 90000 ;'
Counter cascade counts negative edges,
comparison value 90,000
Both counter registers work together as one counter. If the cascading counter exceeds the
comparison value, then:
•
An interrupt is triggered and OB3 is called up, if it has been programmed.
•
Bit 35.0 and bit 35.1 are set to ”1” at the same time in the diagnostic byte (IB 35) independent
of the presence of OB3.
•
The counter is reset to ”0”.
The ”set” bits in the diagnostic byte that flag a counter overflow or reaching of the comparison
value can be reset by using bit operations R I 35.0 and R I 35.1 (see Section 11.2).
Note
You have to reset the counter overflow bits 35.0 and 35.1 in the diagnostic byte to "0"
when the program has completed interrupt processing.
The operating system generally updates the diagnostic byte before calling OB3. Any
new causes of interrupts signalled during OB3 execution are not immediately flagged in
the diagnostic byte. The operating system enters them in the diagnostic byte before
OB3 is called again.
EWA 4NEB 812 6115-02b
11-7
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