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LOGO! Manual
A5E00067781 01
4.2.4 NAND with RLO Edge Detection
Symbol in LOGO!:
The output of NAND with RLO edge detection only adopts
the state 1 when at least one input has the state 0 and all
inputs had the state 1 in the previous cycle.
If an input pin of this block is not wired (x), then the follow-
ing applies to the input: x = 1.
Timing diagram for NAND with RLO edge detection
1
Cycle
3
Q
2
1
2
3
4
5
6
7
8
9
10
4.2.5 OR
The parallel connection of a number of
normally open contacts is represented
in a circuit diagram as follows:
Symbol in LOGO!:
The output of the OR adopts the state 1 if at least one in-
put has the state 1 (i.e. it is closed).
If an input pin of this block is not wired (x), then the follow-
ing applies to the input: x = 0.
LOGO! Functions
