6
External Memory Interface (EMIF)
In order to access an external memory area, an
E
xternal
M
emory
I
nter
F
ace is incorporated in the ERTEC 200. The
interface contains one SDRAM memory controller and one SRAM memory control each for asynchronous memory and
I/O. Both interfaces can be assigned separately as active interfaces. That is, the data bus is driven actively to High at the
end of each access. The internal pull-ups keep the data bus actively at High. External pull-ups are not required. When
writing, this occurs after the end of the strobe phase. When reading, this occurs after a specified time has elapsed after
the end of the strobe phase to avoid driving against the externally read block. For the SDRAM controller, this time is
equivalent to one AHB bus cycle. For the asynchronous controller, the time is equivalent to the time required for the hold
phase to elapse, which corresponds to the time from the rising edge of RD_N to the rising edge of the chip select signal.
By default, the active interface is switched on.
The following signal pins are available for the EMIF on the ERTEC 200.
•
Data bus
32 bit
D[31 : 0]
•
Address bus
24 bit
A[23 : 0]
•
Memory
CS
4
CS_PER0_N - CS_PER3_N
•
Byte
enable
4
BE0_DQM0_N – BE3_DQM3_N
•
RD/WR
Async. 2
RD_N/WR_N
•
Ready
1
RDY_PER_N
•
DIR
2
DTR_N/OE_DRIVER_N
•
SDRAM
5
CLK_SDRAM/CS_SDRAM_N /RAS_SDRAM_N /CAS_SDRAM_N /WE_SDRAM_N
The SDRAM controller has the following features:
16-bit or 32-bit data bus width can be assigned
PC100 SDRAM-compatible (50 Mhz clock frequency)
1 bank with a maximum of 128 Mbytes of SDRAM or
2 banks, each with 64 Mbytes of SDRAM or
4 banks, each with 32 Mbytes of SDRAM for 32-bit data bus width
Supports various SDRAMs with the following properties:
o
CAS latency 2 or 3 clock cycles
o
1/2/4 internal banks can be addressed
(A1 : 0)
o
8/9/10/11 bits column address
(A13, 11:2)
o
Maximum of 13 row addresses
(A14 : 2)
SDRAMS with a maximum of 4 banks are supported. The SDRAM controller can keep all 4 banks open simultaneously.
In terms of addresses, these four banks correspond to one quarter of the SDRAM address area on the AHB bus. As long
as the alternating accesses are in the respective page, no page miss can occur. The refresh counter is always in
operation. Moreover, it cannot be switched off when SDRAM is not being used.
The asynchronous memory controller has the following features:
8-bit, 16-bit, or 32-bit data bus width can be assigned
4 chip selects
Maximum of 16 Mbytes per chip select can be addressed
Different timing can be assigned for each chip select
Ready signal can be assigned differently (synchronous/asynchronous) for each chip select
Chip select CS_PER0_N can be used for a BOOT operation from external memory
Data bus width of the external memory for a BOOT operation is selected via the BOOT[3:0] input pins
Default setting “Slow timing” for BOOT operation
Timeout monitoring can be assigned
Supports the following asynchronous blocks
o
SRAM
o
Flash
PROM
o
External I/O blocks
When setting the asynchronous timing, you must ensure that the access length (with ready control) does not exceed the
duration of 2 SDRAM refresh operations. Failure to do so can cause some refresh operations to be lost. Note that 32-bit
access to blocks that are 8 bits wide requires 4 access attempts. During this time, the SDRAM cannot be refreshed.
Copyright © Siemens AG 2007. All rights reserved.
69
ERTEC 200 Manual
Technical data subject to change
Version 1.1.0
