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CPU to PCI Write Buffer
When this item is enabled, up to four Dwords of data can be written to
the PCI bus without interrupting the CPU. When disabled, a write buffer
is not used and the CPU read cycle will not be completed until the PCI
bus is ready to receive the data.
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The choice: Enabled, Disabled.
PCI Dynamic Bursting
When Enabled, data transfers on the PCI bus, where possible, make
use of the high performance PCI burst protocol, in which greater
amounts of data are transferred at a single command.
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The choice: Enabled, Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus is a command with zero wait tate.
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The choice: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transaction cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The choice: Enabled, Disabled.
PCI #2 Access #1 Retry
This item allows you to enable/disable the PCI #2 Access #1 Retry.
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The choice: Enabled, Disabled.
AGP Master 1 WS Write
This implements a single delay when writing to the AGP Bus. By de-
fault, two wait states are used by the system for greater stability.
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The choice: Enabled, Disabled.
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By
default, two wait states are used by the system for greater stability.
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The choice: Enabled, Disabled.
Memory Parity/ECC Check
This lets you enable or disable memory ECC function. The ECC algo-
rithm has the ability to detect double bit error and automatically correct
single bit error.
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The choice: Enabled, Disabled.
