Sharp ER-A570, Руководство по обслуживанию

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4) Pin Assingment and timing Charts
Pin function will be described for the host and sub system.
(1) Host pin description
1
DB0—DB7 (data bus) Input/Output, 3-state
Pins 54—61
These lines (data bus) are use for hardware flag assignments:
8-bit data write, hardware flag recognition, and 8-bit data read
from the host.
2
RDH (Read from host), Input
Pin 44
An active low signal which is used when the host reads the
hardware flag and 8-bit data through the data bus.
3
WRH (Write from sub), Input
Pin 45
An active low signal which is used when the host writes the
hardware flag and 8-bit data through the data bus.
4
CS (Chip select from host), Input
Pin 51
An active low signal which is used when the host reads or writes
the hardware flag and 8-bit data through the data bus.
5
AB0, AB1(Address bus from host), Input
Pin 62, 64
An input signal used to select the register when the host reads
or writes the hardware flag and 8-bit data through the data bus.
6
DAK (DMA Acknowledge from host), Input
Pin 47
Not used (+5v)
7
DRQRH (DMA Request read to haos), Output
Pin 49
Not used
8
DRQWH (DMA request write to host), Output
Pin 50
Not used
9
TCH (Terminal count from host), Input
Pin 48
Not used
Φ
INTH (Interrupt to host), Output
Pin 46
An active low signal which is used to inform the interrupt signal
that the controller has the information to read or write.
Γ
RES (Reset), Input
Pin 35
Asynchronous reset signal from the host which is used to reset
registers within the controller.
•
HOST read timing.
Fig. 8
•
HOST write timing.
Fig. 9
(2) Sub system pin description
1
D0 – D7 (Data bus) Input Output (3-state)
Pin 32 – 25
These lines (data bus) are used for hardware flag assignments:
8 bit data write, hardware flag recognition, and 8-bit data read
from the subsystem.
2
IORQ (I/O request), Input
Pin 3
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunciton with
RDS, WRS, A0, A1, A4 and A5.
3
MREQ (Memory request), Input
Pin 4
An active low memory request input from the subsystem (Z-80A)
which is used to create I/O control signals in conjunction with
RDS and WRS.
4
RDS (Read from sub), Input
Pin 5
Data read signal received from the subsystem (Z-80A) wihch is
used to create I/O and memory data read control signal.
CS
AB0, AB1
RDH
DB0-DB7
TAR
TRWS
TRA
TRDE TRDF
CS
AB0, AB1
WRH
DB0-DB7
TAW
TWWS
TWA
TDW TWD
4  4