Sharp ER-A570, Руководство по обслуживанию

Страница: 44 / 73

IV. HARDWARE DESCRIPTION FOR ER-A6IN
AND ER-A5RS
CHAPTER1. ER-A6IN
1. Block Diagram
Fig. 1 SRN controller board block diagram
Fig. 1 shows the block diagram of the controller board of the SHARP
RETAIL NETWORK. The Controller is connected to the system bus of
the host system as one of I/O. Inside of the controller consists of Z-80
CPU, transmission link controller, DMA control circuit, ROM, RAM,
modulator, demodulator, carrier detection circuit, collision detect
circuit and so on.
Data communications with the host system is performed by the
handshaking by byte. The controller side functions with DMA (Direct
Memory Access) and is capable of data transmission without waiting
for the host system side.
∗
OPC1 is used only as a bus buffer. (In order to provide compatibil-
ity between the host CPU in the ECR side and H8/510.)
2. CPU Description (Z-80)
For details on the CPU, see the Cash Register Basic Manual.
Pin Connections (C-MOS Version used)
Pin Signal name
Input/
Output
Description
1 A11 Out Address Bus A11
2 A12 Out Address Bus A12
3 A13 Out Address Bus A13
4 A14 Out Address Bus A14
5 A15 Out Address Bus A15
6
φ
In CLK4 (MHz)
7 D4 I/O Data Bus D4
8 D3 I/O Data Bus D3
9 D5 I/O Data Bus D5
10 D6 I/O Data Bus D6
Pin Signal name
Input/
Output
Description
11 VCC — +5V
12 D2 I/O Data Bus D2
13 D7 I/O Data Bus D7
14 D0 I/O Data Bus D0
15 D1 I/O Data Bus D1
16 INT In Interrupt
17 NMI In Non Maskable Interrupt
18 HALT Out HALT
19 MREQ Out Memory Request
20 IOREQ Out I/O Request
21 RD Out Read
22 WR Out Write
23 BUSAK Out Bus acknowledge
24 WAIT In WAIT
25 BUSRQ In Bus Request
26 RES In Reset
27 M1 Out M1 cycle
28 RFSH Out Refresh
29 GND — GND
30 A0 Out Address Bus A0
31 A1 Out Address Bus A1
32 A2 Out Address Bus A2
33 A3 Out Address Bus A3
34 A4 Out Address Bus A4
35 A5 Out Address Bus A5
36 A6 Out Address Bus A6
37 A7 Out Address Bus A7
38 A8 Out Address Bus A8
39 A9 Out Address Bus A9
40 A10 Out Address Bus A10
3. Description of MB62H149
1) Outline
The MB62H149 is a semi-custom LSI chip for the peripheral circuits
in the SRN (SHARP Retail Network), its main function is to
communicate data with the host CPU and control the peripheral
circuits and transmission control circuits of the Sub CPU (Z-80). Fig.
2. shows the general configuration of the functions:
Fig. 2
DATA BUS
CONTROL BUS
BUS BUFFER
D B
CONT
EXTERNAL
CABLE
HOST SYSTEM
BUS
RAM
DMA
CONTROLLER
CARRIER
DETECTION
COLLISION
DETECTION
CPU: Z80
ROM CLOCK
CIRCUIT
MODULATOR
TRANSMISSION
LINK
CONTROLLER
DEMODU-
LATOR
OPC1
MB62H149
Line
TRANS-
MISSION
CONTROL
CIRCUIT
PERIPHERAL
CIRCUIT
DATA HAND
SHAKING
CIRCUIT
TIMER
COUNTER SUB-CPU
(Z-80)
DMAC ADLC
HOST CPU
4  1