SU320CSX
4110-0446, Rev. C
Page 24 of 96
© 2017 UTC
Aerospace Systems
Date Printed: 3-Jan-2017
This document does not contain any export controlled technical data.
Figure 9. Simplified GMOD pixel schematic
The camera frame sequence consists of an exposure followed by digitization and readout. During
exposure, the integration reset switch is open and the integration capacitor shown is discharged from its
reset voltage by the mirrored photodiode current, converting the signal current to a voltage. At the end of
the integration time, the sample switch is momentarily closed to sample the integration period’s final
signal voltage. After the signal is sampled, the integration reset switch is closed and held until the start of
the next integration period. The exposure may or may not overlap the readout of the last frame depending
on the exposure period and the frame rate. Since all pixel’s integration reset, sample, and sample reset
switches receive the same clock timing, the FPA operates with “snapshot” exposure: all pixels are
exposed simultaneously, starting and finishing at the same time.
In order to generate the serial digital video signal that is output from the FPA, each row is sequentially
selected, and the analog pixel signals are passed to circuitry at the edge of the array. An on-ROIC ADC
converts the pixel signals to 12-bit digital values, which are then serialized and output on a high speed
digital bus.
4.2.
Camera System Operation
The CSX camera provides all support functions to the SU320AB4 focal plane array necessary to provide
the user access to its full performance capabilities. The camera is a complete data acquisition system
supporting the analog, digital, and power conditioning subsystems needed to operate the focal plane array
with minimal external support, with digital taps available to grab the signal at various stages. A basic
signal flow diagram for the CSX camera system is shown.
