
COMe-cWL6 – User Guide Rev. 1.4
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2.3.22.
External Fan support
Table 28: External Fan Control
COMe Signal
HWM Pin
FAN_PWMOUT
FANCTL2
FAN_TACHIN
FANIN2
2.3.23.
General Purpose PCI Express 3.0
Table 29: General Purpose PCI Express 3.0
COMe connector
PCH HSIO
Function
Lane Config
Intel RST/Optane
PCIE0
PCIE5
x1
x4
NO
PCIE1
PCIE6
x1
PCIE2
PCIE7
x1
PCIE3
PCIE8
x1
PCIE4
PCIE10
NO
PCIE5 (no GbE)
PCIE9
PCIE6 (no SATA0)
PCIE11
x1
PCIE7 (no SATA1)
PCIE12
x1
PEG0
PCIE13
x1
x4
YES
PEG1
PCIE14
x1
PEG2 (no NVME)
PCIE15
x1
PEG3 (no NVME/
no SATA2)
PCIE16
x1
2.3.24.
Universal Serial Bus (USB)
For every USB 3.1 port, one USB2 and one USB31 lane has to be bonded. Therefore the number of available USB 2.0
ports decreases with every used 3.1 port. The SoC offers the following configurations:
Up to 8x USB 2.0
Up to 4x USB 3.1 with 10 Gbit/s
Table 30: USB
COMe USB2
COMe USB3
PCH USB2
PCH USB31
USB0
USB_SS0
USB2_1
USB31_1
USB1
USB_SS1
USB2_2
USB31_2
USB2
USB_SS2
USB2_3
USB31_3
USB3
USB_SS3
USB2_4
USB31_4
USB4
-
USB2_5
-
USB5
-
USB2_6
-
USB6
-
USB2_7
-
USB7
-
USB2_8
-