COMe-cWL6 – User Guide Rev. 1.4
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2.3.9.
I2C Bus
Two I2C Buses are generated by FPGA’s internal kCPLD block:
1. External user-accessible I2C connected to embedded EEPROM and COM Express connector.
2. Internal on-module I2C connected to VGA-bridge, LVDS-bridge, external LVDS-DDC-interface and S5-ECO
switch.
2.3.10.
SMBus
SMBbus on COMe connector is shared with onboard devices, so special care must be taken while selecting addresses
for carrier devices.
Reserved addresses are:
A0h : DDR4 Channel A SPD EEPROM (SO-DIMM)
A4h: DDR4 Channel B SPD EEPROM (memory down)
30h: DDR4 Channel A optional Temperature Sensor (SO-DIMM)
5Ch: Hardware Monitor
2.3.11.
Wake Signals
Table 19: Wake Signals
COMe Signal
PCH Pin
Description
WAKE0#
WAKE#
PCI Express wake signal
WAKE1#
GPP_C6
General purpose wake signal
2.3.12.
Suspend Control
Table 20: Suspend Control
COMe Signal
PCH Pin
Description
SUS_STAT#/ESPI_RESET#
SUS_STAT#/ESPI_RESET#
SUS_S3#
SLP_S3#
passed through FPGA/EC
SUS_S4#
SLP_S4#
SUS_S5#
SLP_S5#
2.3.13.
System Reset (SYS_RESET#)
Table 21: System Reset (SYS_RESET#)
COMe Signal
PCH Pin
Description
SYS_RESET#
SYS_RESET
Input from carrier. Passed through FPGA/EC
2.3.14.
Carrier Board Reset (CB_RESET#)
Output to carrier. Derived from PLTRST# in FPGA/EC.